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february 2012 doc id 14733 rev 12 1/103 1 stm8s207xx stm8s208xx performance line, 24 mhz stm8s 8- bit mcu, up to 128 kb flash, integrated eeprom, 10-bit adc, timers, 2 uarts, spi, i2c, can features core ?max f cpu : up to 24 mhz, 0 wait states @ f cpu 16 mhz ? advanced stm8 core with harvard architecture and 3-stage pipeline ? extended instruction set ? max 20 mips @ 24 mhz memories ? program: up to 128 kbytes flash; data retention 20 years at 55 c after 10 kcycles ? data: up to 2 kbytes true data eeprom; endurance 300 kcycles ? ram: up to 6 kbytes clock, reset and supply management ? 2.95 to 5.5 v operating voltage ? low power crystal resonator oscillator ? external clock input ? internal, user-trimmable 16 mhz rc ? internal low power 128 khz rc ? clock security system with clock monitor ? wait, active-halt, & halt low power modes ? peripheral clocks switched off individually ? permanently active, low consumption power-on and power-down reset interrupt management ? nested interrupt controller with 32 interrupts ? up to 37 external interrupts on 6 vectors timers ? 2x 16-bit general purpose timers, with 2+3 capcom channels (ic, oc or pwm) ? advanced control timer: 16-bit, 4 capcom channels, 3 complementary outputs, dead- time insertion and flexible synchronization ? 8-bit basic timer with 8-bit prescaler ? auto wakeup timer ? window watchdog, independent watchdog communications interfaces ? high speed 1 mbit/s active becan 2.0b ? uart with clock output for synchronous operation - lin master mode ? uart with lin 2.1 compliant, master/slave modes and automatic resynchronization ? spi interface up to 10 mbit/s ?i 2 c interface up to 400 kbit/s 10-bit adc with up to 16 channels i/os ? up to 68 i/os on an 80-pin package including 18 high sink outputs ? highly robust i/o design, immune against current injection ? development support ? single wire interface module (swim) and debug module (dm) 96-bit unique id key for each device table 1. device summary part numbers: stm8s207xx stm8s207mb, stm8s2 07m8, stm8s207rb, stm8s207r8, stm8s2 07r6, stm8s207cb, stm8s207c8, stm8s2 07c6, stm8s207sb, stm8s207s8, stm8s2 07s6, stm8s207k8 stm8s207k6 part numbers: stm8s208xx stm8s208mb, stm8s2 08m8, stm8s208rb, stm8s208r8, stm8s2 08r6, stm8s208cb, stm8s208c8, stm8s2 08c6, stm8s208sb, stm8s208s8, stm8s208s6 lqfp80 14x14 lqfp64 10x10 lqfp32 7x7 lqfp44 10x10 lqfp64 14x14 lqfp48 7x7 www.st.com
contents stm8s207xx, stm8s208xx 2/103 doc id 14733 rev 12 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 central processing unit stm8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 single wire interface module (swim) and debug module (dm) . . . . . . . . 14 4.3 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 flash program and data eeprom memory . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.7 watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.9 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.10 tim1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.11 tim2, tim3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 18 4.12 tim4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.13 analog-to-digital converter (adc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14.1 uart1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14.2 uart3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14.3 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.14.4 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.14.5 becan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
stm8s207xx, stm8s208xx contents doc id 14733 rev 12 3/103 6.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9 unique id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.4 typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1.5 pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.6 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.7 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.3.1 vcap external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.3.2 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.3.3 external clock sources and timing characteristics . . . . . . . . . . . . . . . . . 64 10.3.4 internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 66 10.3.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.3.6 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.3.7 reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.3.8 spi serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.3.9 i 2 c interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.3.10 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.1.1 lqfp package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 96
contents stm8s207xx, stm8s208xx 4/103 doc id 14733 rev 12 12 stm8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.1 emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.2 software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.2.1 stm8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.2.2 c and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.3 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
stm8s207xx, stm8s208xx list of tables doc id 14733 rev 12 5/103 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm8s20xxx performance line features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. peripheral clock gating bit assignments in clk_ pckenr1/2 registers . . . . . . . . . . . . . . . 16 table 4. tim timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. legend/abbreviations for pinout table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 7. flash, data eeprom and ram b oundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 8. i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 9. general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 10. cpu/swim/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 11. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 12. option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 13. option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 14. unique id registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 15. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 16. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 17. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 18. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 19. operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 20. total current consumption with code execution in run mode at v dd = 5 v. . . . . . . . . . . . . 57 table 21. total current consumption with code execution in run mode at v dd = 3.3 v . . . . . . . . . . . 58 table 22. total current consumption in wait mode at v dd = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 23. total current consumption in wait mode at v dd = 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 24. total current consumption in active halt mode at v dd = 5 v, t a -40 to 85 c . . . . . . . . . . 60 table 25. total current consumption in active halt mode at v dd = 3.3 v . . . . . . . . . . . . . . . . . . . . . . 60 table 26. total current consumption in halt mode at v dd = 5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 27. total current consumption in halt mode at v dd = 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 28. wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 29. total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 62 table 30. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 31. hse user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 table 32. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 33. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 34. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 35. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 36. flash program memory/data eeprom memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 37. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 38. output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 39. output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 40. output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 41. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 42. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 43. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 44. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 45. adc accuracy with r ain < 10 k , v dda = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 46. adc accuracy with r ain < 10 k r ain , v dda = 3.3 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 47. ems data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 48. emi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
list of tables stm8s207xx, stm8s208xx 6/103 doc id 14733 rev 12 table 49. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 50. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 51. 80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 52. 64-pin low profile quad flat package mechanical data (14 x 14) . . . . . . . . . . . . . . . . . . . . . 90 table 53. 64-pin low profile quad flat package mechanical data (10 x 10) . . . . . . . . . . . . . . . . . . . . . 91 table 54. 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 55. 44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 56. 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 57. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 58. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
stm8s207xx, stm8s208xx list of figures doc id 14733 rev 12 7/103 list of figures figure 1. stm8s20xxx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. flash memory organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. lqfp 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4. lqfp 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. lqfp 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 6. lqfp 44-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7. lqfp 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 9. supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 10. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 11. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 12. f cpumax versus v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 13. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 14. typ. i dd(run) vs v dd , hsi rc osc, f cpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 15. typ. i dd(wfi) vs v dd , hsi rc osc, f cpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 16. hse external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 17. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 18. typical hsi frequency variation vs v dd at 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 19. typical lsi frequency variation vs v dd @ 25 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 20. typical v il and v ih vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 21. typical pull-up resistance vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 22. typical pull-up current vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 23. typ. v ol @ v dd = 5 v (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 24. typ. v ol @ v dd = 3.3 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 25. typ. v ol @ v dd = 5 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 26. typ. v ol @ v dd = 3.3 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 27. typ. v ol @ v dd = 5 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 28. typ. v ol @ v dd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 29. typ. v dd - v oh @ v dd = 5 v (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 30. typ. v dd - v oh @ v dd = 3.3 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 31. typ. v dd - v oh @ v dd = 5 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 32. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 33. typical nrst v il and v ih vs v dd @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 34. typical nrst pull-up resistance vs v dd @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 76 figure 35. typical nrst pull-up current vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 36. recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 37. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 38. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 39. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 40. typical application with i 2 c bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 41. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 42. typical application with adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 43. 80-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 44. 64-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 45. 64-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 46. 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 47. 44-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 48. 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
list of figures stm8s207xx, stm8s208xx 8/103 doc id 14733 rev 12 figure 49. stm8s207xx/208xx performance line ordering information scheme (1) . . . . . . . . . . . . . . . 99
stm8s207xx, stm8s208xx introduction doc id 14733 rev 12 9/103 1 introduction this datasheet contains the description of the stm8s20xxx performance line features, pinout, electrical characteristics, mech anical data and ordering information. for complete information on the stm8s microcontroller memory, registers and peripherals, please refer to the stm8s microcontroller family reference manual (rm0016). for information on programming, erasing and protection of the internal flash memory please refer to the stm8s flash programming manual (pm0051). for information on the debug and swim (single wire interface module) refer to the stm8 swim communication protocol and debug module user manual (um0470). for information on the stm8 core, please refer to the stm8 cpu programming manual (pm0044).
description stm8s207xx, stm8s208xx 10/103 doc id 14733 rev 12 2 description the stm8s20xxx performance line 8-bit microcontrollers offer from 32 to 128 kbytes flash program memory. they are referred to as high-density devices in the stm8s microcontroller family reference manual. all devices of the stm8s20xxx performance line provide the following benefits: reduced system cost, performance robustness, short development cycles, and product longevity. the system cost is reduced thanks to an integrated true data eeprom for up to 300 k write/erase cycles and a high system integration level with internal clock oscillators, watchdog, and brown-out reset. device performance is ensured by 20 mips at 24 mhz cpu clock frequency and enhanced characteristics which include robust i/o, independent watchdogs (with a separate clock source), and a clock security system. short development cycles are g uaranteed due to app lication scalability across a common family product architecture with compatible pinout, memory map and and modular peripherals. full documentation is offered with a wide choice of development tools. product longevity is ensured in the stm8s fam ily thanks to their advanced core which is made in a state-of-the art technology for applications with 2.95 v to 5.5 v operating supply.
stm8s207xx, stm8s208xx description doc id 14733 rev 12 11/103 table 2. stm8s20xxx performance line features device pin count max. number of gpios (i/o) ext. interrupt pins timer capcom channels timer complementary outputs a/d converter channels high sink i/os high density flash program memory (bytes) data eeprom (bytes ram (bytes) becan interface stm8s207mb stm8s207m8 stm8s207rb stm8s207r8 stm8s207r6 stm8s207cb stm8s207c8 stm8s207c6 stm8s207sb stm8s207s8 stm8s207s6 stm8s207k8 stm8s207k6 80 80 64 64 64 48 48 48 44 44 44 32 32 68 68 52 52 52 38 38 38 34 34 34 25 25 37 37 36 36 36 35 35 35 31 31 31 23 23 9 9 9 9 9 9 9 9 8 8 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 16 16 16 16 16 10 10 10 9 9 9 7 7 18 18 16 16 16 16 16 16 15 15 15 12 12 128 k 64 k 128 k 64 k 32 k 128 k 64 k 32 k 128 k 64 k 32 k 64 k 32 k 2048 2048 2048 1536 1024 2048 1536 1024 1536 1536 1024 1024 1024 6 k 6 k 6 k 6 k 6 k 6 k 6 k 6 k 6 k 6 k 6 k 6 k 6 k no stm8s208mb stm8s208rb stm8s208r8 stm8s208r6 stm8s208cb stm8s208c8 stm8s208c6 stm8s208sb stm8s208s8 stm8s208s6 80 64 64 64 48 48 48 44 44 44 68 52 52 52 38 38 38 34 34 34 37 37 37 37 35 35 35 31 31 31 9 9 9 9 9 9 9 8 8 8 3 3 3 3 3 3 3 3 3 3 16 16 16 16 10 10 10 9 9 9 18 16 16 16 16 16 16 15 15 15 128 k 128 k 64 k 32 k 128 k 64 k 32 k 128 k 64 k 32 k 2048 2048 2048 2048 2048 2048 2048 1536 1536 1536 6 k 6 k 6 k 6 k 6 k 6 k 6 k 6 k 6 k 6 k ye s
block diagram stm8s207xx, stm8s208xx 12/103 doc id 14733 rev 12 3 block diagram figure 1. stm8s20xxx performance line block diagram 1. legend: adc: analog-to-digital converter becan: controller area network bor: brownout reset i2c: inter-integrated circuit multimaster interface independent wdg: independent watchdog por/pdr: power on reset / power down reset spi: serial peripheral interface swim: single wire interface module uart: universal asynchr onous receiver transmitter window wdg: window watchdog xtal 1-24 mhz rc int. 16 mhz rc int. 128 khz stm8 core debug/swim i 2 c spi uart1 uart3 awu timer reset block reset clock controller detector clock to peripherals and core 10 mbit/s lin master 16 channels address and data bus window wdg up to 128 kbytes up to 2 kbytes up to 6 kbytes boot rom adc2 becan reset 400 kbit/s 1 mbit/s master/slave single wire autosynchro debug interf. spi emul. high density program flash data eeprom ram 16-bit general purpose 16-bit advanced control timer (tim1) timers (tim2, tim3) 8-bit basic timer (tim4) beeper 1/2/4 khz beep independent wdg 4 capcom channels up to 5 capcom channels up to + 3 complementary outputs por/pdr bor
stm8s207xx, stm8s208xx product overview doc id 14733 rev 12 13/103 4 product overview the following section intends to give an overview of the basic features of the stm8s20xxx performance line functional modules and peripherals. for more detailed information please refer to the corresponding family reference manual (rm0016). 4.1 central processing unit stm8 the 8-bit stm8 core is designed for code efficiency and performance. it contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. architecture and registers harvard architecture 3-stage pipeline 32-bit wide program memory bus - single cycle fetching for most instructions x and y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter - 16-mbyte linear memory space 16-bit stack pointer - access to a 64 k-level stack 8-bit condition code register - 7 condition flags for the result of the last instruction addressing 20 addressing modes indexed indirect addressing mode for look-up tables located anywhere in the address space stack pointer relative addressing mode for local variables and parameter passing instruction set 80 instructions with 2-byte average instruction size standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division bit manipulation data transfer between stack and accumulator (push/pop) with direct stack access data transfer using the x and y registers or direct memory-to-memory transfers
product overview stm8s207xx, stm8s208xx 14/103 doc id 14733 rev 12 4.2 single wire interface module (swim) and debug module (dm) the single wire interface module and debug module permits non-intrusive, real-time in- circuit debugging and fast memory programming. swim single wire interface module for direct access to the debug module and memory programming. the interface can be activated in all device operation modes. the maximum data transmission speed is 145 bytes/ms. debug module the non-intrusive debugging module features a performance close to a full-featured emulator. beside memory and peripherals, also cpu operation can be monitored in real- time by means of shadow registers. r/w to ram and peripheral registers in real-time r/w access to all resources by stalling the cpu breakpoints on all program-memory instructions (software breakpoints) two advanced breakpoints, 23 predefined configurations 4.3 interrupt controller nested interrupts with three software priority levels 32 interrupt vectors with hardware priority up to 37 external interrupts on six vectors including tli trap and reset interrupts 4.4 flash program and data eeprom memory up to 128 kbytes of high density flash program single voltage flash memory up to 2k bytes true data eeprom read while write: writing in data memory possible while executing code in program memory. user option byte area write protection (wp) write protection of flash program memory and data eeprom is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. there are two levels of write protection. the first level is known as mass (memory access security system). mass is always enabled and protec ts the main flash program memory, data eeprom and option bytes. to perform in-application programming (iap), this write protection can be removed by writing a mass key sequence in a control register. this allows the application to write to data eeprom, modify the contents of main program memory or the device option bytes. a second level of write protection, can be enabled to further protect a specific area of memory known as ubc (user boot code). refer to figure 2 .
stm8s207xx, stm8s208xx product overview doc id 14733 rev 12 15/103 the size of the ubc is programmable through the ubc option byte ( table 13. ), in increments of 1 page (512 bytes) by programming the ubc option byte in icp mode. this divides the program memory into two areas: main program memory: up to 128 kbytes minus ubc user-specific boot code (ubc): configurable up to 128 kbytes the ubc area remains write-protected during in-application programming. this means that the mass keys do not unlock the ubc area. it protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the iap and communication routines. figure 2. flash memory organisation read-out protection (rop) the read-out protection blocks reading and writing the flash program memory and data eeprom memory in icp mode (and debug mode). on ce the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. programmable area from 1 kbyte data ubc area program memory area data memory area (2 kbytes) (2 first pages) up to 128 kbytes eeprom remains write protected during iap memory 128 kbytes flash up to write access possible for iap program memory (1 page steps) option bytes
product overview stm8s207xx, stm8s208xx 16/103 doc id 14733 rev 12 4.5 clock controller the clock controller distributes the system clock (f master) coming from different oscillators to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. features clock prescaler : to get the best compromise between speed and current consumption the clock frequency to the cp u and peripherals can be adjusted by a programmable prescaler. safe clock switching : clock sources can be changed safely on the fly in run mode through a configuration register. the clock signal is not switched until the new clock source is ready. the design guarantees glitch-free switching. clock management : to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. master clock sources : four different clock sources can be used to drive the master clock: ? 1-24 mhz high-speed external crystal (hse) ? up to 24 mhz high-speed user-external clock (hse user-ext) ? 16 mhz high-speed intern al rc oscillator (hsi) ? 128 khz low-speed internal rc (lsi) startup clock : after reset, the microcontroller restarts by default with an internal 2 mhz clock (hsi/8). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. clock security system (css) : this feature can be enabled by software. if an hse clock failure occurs, the internal rc (16 mhz/ 8) is automatically selected by the css and an interrupt can optionally be generated. configurable main clock output (cco) : this outputs an external clock for use by the application. table 3. peripheral clock gating bit assignments in clk_pckenr1/2 registers bit peripheral clock bit peripheral clock bit peripheral clock bit peripheral clock pcken17 tim1 pcken13 uart3 pcken27 becan pcken23 adc pcken16 tim3 pcken12 uart1 pcken26 reserved pcken22 awu pcken15 tim2 pcken11 spi pcken25 reserved pcken21 reserved pcken14 tim4 pcken10 i 2 c pcken24 reserved pcken20 reserved
stm8s207xx, stm8s208xx product overview doc id 14733 rev 12 17/103 4.6 power management for efficent power management, the application can be put in one of four different low-power modes. you can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. wait mode : in this mode, the cpu is stopped, but peripherals are kept running. the wakeup is performed by an internal or external interrupt or reset. active halt mode with regulator on : in this mode, the cpu and peripheral clocks are stopped. an internal wakeup is generated at programmable intervals by the auto wake up unit (awu). the main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. wakeup is triggered by the internal awu interrupt, external interrupt or reset. active halt mode with regulator off: this mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower. halt mode : in this mode the microcontroller uses the least power. the cpu and peripheral clocks are stopped, the main voltage regulator is powered off. wakeup is triggered by external event or reset. 4.7 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. activation of the watchdog timers is controlled by option bytes or by software. once activated, the watchdogs cannot be disabled by the user program without performing a reset. window watchdog timer the window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. the window function can be used to trim the watchdog behavior to match the application perfectly. the application software must refresh the counter before time-out and during a limited time window. a reset is generated in two situations: 1. timeout: at 16 mhz cpu clock the time-out period can be adjusted between 75 s up to 64 ms. 2. refresh out of window: the downcounter is refreshed before its value is lower than the one stored in the window register.
product overview stm8s207xx, stm8s208xx 18/103 doc id 14733 rev 12 independent watchdog timer the independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the 128 khz lsi internal rc cloc k source, and thus stays active even in case of a cpu clock failure the iwdg time base spans from 60 s to 1 s. 4.8 auto wakeup counter used for auto wakeup from active halt mode clock source: internal 128 khz internal lo w frequency rc oscillator or external clock lsi clock can be internally connected to tim3 input capture channel 1 for calibration 4.9 beeper the beeper functi on outputs a signal on the beep pin for sound gener ation. the signal is in the range of 1, 2 or 4 khz. 4.10 tim1 - 16-bit advanced control timer this is a high-end timer designed for a wide range of control applications. with its complementary outputs, dead-ti me control and center-aligned pwm capability, the field of applications is extended to motor control, lighting and half-bridge driver 16-bit up, down and up/down autoreload counter with 16-bit prescaler four independent capture/compare channels (capcom) configurable as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output synchronization module to control the timer with external signals break input to force the timer outputs into a defined state three complementary outputs with adjustable dead time encoder mode interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break 4.11 tim2, tim3 - 16-bit general purpose timers 16-bit autoreload (ar) up-counter 15-bit prescaler adjustable to fixed power of 2 ratios 1?32768 timers with 3 or 2 individually configurable capture/compare channels pwm mode interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
stm8s207xx, stm8s208xx product overview doc id 14733 rev 12 19/103 4.12 tim4 - 8-bit basic timer 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 clock source: cpu clock interrupt source: 1 x overflow/update 4.13 analog-to-digital converter (adc2) stm8s20xxx performance line products contain a 10-bit successive approximation a/d converter (adc2) with up to 16 multiplexed input channels and the following main features: input voltage range: 0 to v dda dedicated voltage reference (vref) pins available on 80 and 64-pin devices conversion time: 14 clock cycles single and continuous modes external trigger input trigger from tim1 trgo end of conversion (eoc) interrupt 4.14 communication interfaces the following communication interfaces are implemented: uart1: full feature uart, spi emulation, lin2.1 master capabilit y, smartcard mode, irda mode, single wire mode. uart3: full feature uart, lin2.1 master/slave capability spi : full and half-duplex, 10 mbit/s i2c: up to 400 kbit/s becan (rev. 2.0a,b) - 3 tx mailboxes - up to 1 mbit/s table 4. tim timer features timer counter size (bits) prescaler counting mode capcom channels complem. outputs ext. trigger timer synchr- onization/ chaining tim1 16 any integer from 1 to 65536 up/down 4 3 yes no tim2 16 any power of 2 from 1 to 32768 up 3 0 no tim3 16 any power of 2 from 1 to 32768 up 2 0 no tim4 8 any power of 2 from 1 to 128 up 0 0 no
product overview stm8s207xx, stm8s208xx 20/103 doc id 14733 rev 12 4.14.1 uart1 main features one mbit/s full duplex sci spi emulation high precision baud rate generator smartcard emulation irda sir encoder decoder lin master mode single wire half duplex mode asynchronous communication (uart mode) full duplex communication - nrz standard format (mark/space) programmable transmit and receive baud rates up to 1 mbit/s (f cpu /16) and capable of following any standard baud rate regardless of the input frequency separate enable bits for transmitter and receiver two receiver wakeup modes: ? address bit (msb) ? idle line (interrupt) transmission error detection with interrupt generation parity control synchronous communication full duplex synchronous transfers spi master operation 8-bit data communication maximum speed: 1 mbit/s at 16 mhz (f cpu /16) lin master mode emission: generates 13-b it synch break frame reception: detects 11-bit break frame 4.14.2 uart3 main features 1 mbit/s full duplex sci lin master capable high precision baud rate generator
stm8s207xx, stm8s208xx product overview doc id 14733 rev 12 21/103 asynchronous communication (uart mode) full duplex communication - nrz standard format (mark/space) programmable transmit and receive baud rates up to 1 mbit/s (f cpu /16) and capable of following any standard baud rate regardless of the input frequency separate enable bits for transmitter and receiver two receiver wakeup modes: ? address bit (msb) ? idle line (interrupt) transmission error detection with interrupt generation parity control lin master capability emission: generates 13-b it synch break frame reception: detects 11-bit break frame lin slave mode autonomous header handling - one single interrupt per valid message header automatic baud rate synchronization - maximum tolerated initial clock deviation 15 % synch delimiter checking 11-bit lin synch break detection - break detection always active parity check on the lin identifier field lin error management hot plugging support 4.14.3 spi maximum speed: 10 mbit/s (f master /2) both for master and slave full duplex synchronous transfers simplex synchronous transfers on two lines with a possible bidirectional data line master or slave operation - selectable by hardware or software crc calculation 1 byte tx and rx buffer slave/master selection input pin
product overview stm8s207xx, stm8s208xx 22/103 doc id 14733 rev 12 4.14.4 i 2 c i 2 c master features: ? clock generation ? start and stop generation i 2 c slave features: ? programmable i 2 c address detection ? stop bit detection generation and detection of 7-bit/10-bit addressing and general call supports different communication speeds: ? standard speed (up to 100 khz) ? fast speed (up to 400 khz) 4.14.5 becan the becan controller (basic enhanced can), in terfaces the can network and supports the can protocol version 2.0a and b. it has been designed to manage a high number of incoming messages efficiently with a minimum cpu load. for safety-critical applications the becan co ntroller provides all hardware functions to support the can time triggered communication option (ttcan). the maximum transmission speed is 1 mbit. transmission three transmit mailboxes configurable transmit priority by identifier or order request time stamp on sof transmission reception 8-, 11- and 29-bit id one receive fifo (3 messages deep) software-efficient mailbox mapping at a unique address space fmi (filter match index) stored with message configurable fifo overrun time stamp on sof reception six filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking configurations, such as 12 filters for 29-bit id or 48 filters for 11-bit id filtering modes: ? mask mode permitting id range filtering ? id list mode time triggered communication option ? disable automatic retransmission mode ? 16-bit free running timer ? configurable timer resolution ? time stamp sent in last two data bytes
stm8s207xx, stm8s208xx pinouts and pin description doc id 14733 rev 12 23/103 5 pinouts and pin description 5.1 package pinouts figure 3. lqfp 80-pin pinout 1. (hs) high sink capability. 2. (t) true open drain (p-buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate f unction is shown twice, it indicates an exclusive choice not a duplication of the function). 4. can_rx and can_tx is available on stm8s208xx devices only. pd4 (hs)/tim2_ch1 [beep] 2 1 3 4 5 6 7 8 10 9 12 14 16 18 20 11 15 13 17 19 25 26 28 27 30 32 34 36 38 29 33 31 35 37 39 57 58 56 55 54 53 52 51 49 50 47 45 43 41 48 44 46 42 60 59 61 62 63 64 66 68 65 67 69 70 71 72 74 73 75 76 77 78 79 80 pi4 pi3 pi2 pi1 pc4 (hs)/tim1_ch4 pc3 (hs)/tim1_ch3 pc2 (hs)/tim1_ch2 pc1 (hs)/tim1_ch1 pg6 pg5 pi5 pi0 pg4 pg3 pg2 pc7 (hs)/spi_miso v ssio_2 v ddio_1 [tim3_ch1] tim2_ch3/pa3 uart1_rx/ (hs) pa4 uart1_tx/ (hs) pa5 ain12/pf4 v ssio_1 v ss vcap v dd uart1_ck/ (hs) pa6 (hs) ph0 ( hs) ph1 ph2 ph3 ain15/pf7 ain14/pf6 ain13/pf5 nrst oscin/pa1 oscout/pa2 [i2c_sda] ain5/pb5 [i2c_scl] ain4/pb4 [tim1_ch2n] ain1/pb1 [tim1_ch1n] ain0/pb0 ain8/pe7 v ref- ain10/pf0 ain7/pb7 ain6/pb6 tim1_etr/ph4 tim1_ch3n/ph5 tim1_ch2n/ph6 40 ain9/pe6 21 22 24 23 ain11/pf3 v ref+ v dda v ssa pd0 (hs)/tim3_ch2 [tim1_bkin] [clk_cco] pe2 (t]/i 2c_sda pe3/tim1_bkin pe4 pg7 pd7/tli pd6/uart3_rx pd5/uart3_tx pi7 pi6 pd2 (hs)/tim3_ch1 [tim2_ch3] pd1 (hs)/swim pc5 (hs)/spi_sck pc6 (hs)/spi_mosi pg0/can_tx pg1/can_rx pe0 (hs)/clk_cco pd3 (hs)/tim2_ch2 [adc_etr] [tim1_etr] ain3/pb3 [tim1_ch3n] ain2/pb2 pc0/adc_etr pe5/spi_nss tim1_ch1n/ph7 v ddio_2 pe1(t)/i2c_scl
pinouts and pin description stm8s207xx, stm8s208xx 24/103 doc id 14733 rev 12 figure 4. lqfp 64-pin pinout 1. (hs) high sink capability. 2. (t) true open drain (p-buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate f unction is shown twice, it indicates an exclusive choice not a duplication of the function). 4. can_rx and can_tx is available on stm8s208xx devices only. v ref- ain10/pf0 ain7/pb7 ain6/pb6 [i2c_sda] ain5/pb5 [i2c_scl] ain4/pb4 [tim1_etr] ain3/pb3 [tim1_ch3n] ain2/pb2 [tim1_ch2n] ain1/pb1 [tim1_ch1n] ain0/pb0 ain8/pe7 ain9/pe6 ain11/pf3 v ref+ v dda v ssa 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v ss vcap v dd v ddio_1 [tim3_ch1] tim2_ch3/pa3 uart1_rx/ (hs) pa4 uart1_tx/ (hs) pa5 uart1_ck/ (hs) pa6 ain15/pf7 ain14/pf6 ain13/pf5 ain12/pf4 nrst oscin/pa1 oscout/pa2 v ssio_1 pg1/can_rx pg0/can_tx pc7 (hs)/spi_miso pc6 (hs)/spi_mosi v ddio_2 v ssio_2 pc5 (hs)/spi_sck pc4 (hs)/tim1_ch4 pc3 (hs)/tim1_ch3 pc2 (hs)/tim1_ch2 pc1 (hs)/tim1_ch1 pe5/spi_nss pi0 pg4 pg3 pg2 pd3 (hs)/tim2_ch2[adc_etr] pd2 (hs)/tim3_ch1[tim2_ch3] pd1 (hs)/swim pd0 (hs)/tim3_ch2 [tim1_bkin] [clk_cco] pe0 (hs)/clk_cco pe1 (t)/i2c_scl pe2 (t)/i2c_sda pe3/tim1_bkin pe4 pg7 pg6 pg5 pd7/tli pd6/uart3_rx pd5/uart3_tx pd4 (hs)/tim2_ch1 [beep]
stm8s207xx, stm8s208xx pinouts and pin description doc id 14733 rev 12 25/103 figure 5. lqfp 48-pin pinout 1. (hs) high sink capability. 2. (t) true open drain (p-buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate f unction is shown twice, it indicates an exclusive choice not a duplication of the function). 4. can_rx and can_tx is available on stm8s208xx devices only. 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 uart1_ck/(hs) pa6 ain8/pe7 pc1 (hs)/tim1_ch1 pe5/spi_nss pg1/can_rx ain9/pe6 pd3 (hs)/tim2_ch2 [adc_etr] pd2 (hs)/tim3_ch1 [tim2_ch3] pe0 (hs)/clk_cco pe1 (t)/i2c_scl pe2 (t)/i2c_sda pe3/tim1_bkin pd7/tli pd6/uart3_rx pd5/uart3_tx pd4 (hs)/tim2_ch1 [beep] pd1 (hs)/swim pd0 (hs)/tim3_ch2 [tim1_bkin] [clk_cco] v ssio_2 pc5 (hs)/spi_sck pc4 (hs)/tim1_ch4 pc3 (hs)/tim1_ch3 p c2 (hs)/tim1_ch2 pg0/can_tx pc7 (hs)/spi_miso pc6 (hs)/spi_mosi v ddio_2 ain7/pb7 ain6/pb6 [i2c_sda] ain5/pb5 [i2c_scl] ain4/pb4 [tim1_etr/ain3/pb3 [tim1_ch3n] ain2/pb2 [tim1_ch2n] ain1/pb1 [tim1_ch1n] ain0/pb0 v dda v ssa v ss vcap v dd v ddio_1 [tim3_ch1] tim2_ch3/pa3 uart1_rx/(hs) pa4 uart1_tx/(hs) pa5 nrst oscin/pa1 oscout/pa2 v ssio_1
pinouts and pin description stm8s207xx, stm8s208xx 26/103 doc id 14733 rev 12 figure 6. lqfp 44-pin pinout 1. (hs) high sink capability. 2. (t) true open drain (p-buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate f unction is shown twice, it indicates an exclusive choice not a duplication of the function). 4. can_rx and can_tx is available on stm8s208xx devices only. ain6/pb6 [i2c_sda] ain5/pb5 [i2c_scl] ain4/pb4 [tim1_etr] ain3/pb3 [tim1_ch3n] ain2/pb2 [tim1_ch2n] ain1/pb1 (t im1_ch1n] ain0/pb0 ain9/pe6 v dda v ssa ain7/pb7 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 v ss vcap v dd v ddio_1 uart1_rx/ uart1_tx/ uart1_ck/ nrst oscin/pa1 oscout/pa2 v ssio_1 v ddio_2 v ssio_2 pc5 (hs)/spi_sck pc3 (hs)/tim1_ch3 pc2 (hs)/tim1_ch2 pc1 (hs)/tim1_ch1 pe5/spi_nss pg1/can_rx pg0/can_tx pc7 (hs)/spi_miso pc6 (hs)/spi_mosi pd3 (hs)/tim2_ch2 [adc_etr] p d2 (hs)/tim3_ch1 [tim2_ch3] pd1 (hs)/swim pe1 (t)/i2c_scl pe2 (t)/i2c_sda pd7/tli [tim1_ch4] pd6/uart3_rx pd5/uart3_tx pd4 (hs)/tim2_ch1[beep] pe0 (hs)/clk_cco pd0 (hs)/tim3_ch2 [tim1_bkin] [clk_cco]
stm8s207xx, stm8s208xx pinouts and pin description doc id 14733 rev 12 27/103 figure 7. lqfp 32-pin pinout 1. (hs) high sink capability. 2. [ ] alternate function remapping option (if the same alternate f unction is shown twice, it indicates an exclusive choice not a duplication of the function). [i2c_scl] ain4/pb4 [tim1_etr] ain3/pb3 [tim1_ch3n] ain2/pb2 [tim1_ch2n] ain1/pb1 [tim1_ch1n] ain0/pb0 v dda v ssa [i2c_sda] ain5/pb5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10111213141516 1 2 3 4 5 6 7 8 vcap v dd v ddio ain12/pf4 nrst oscin/pa1 oscout/pa2 v ss pc3 (hs)/tim1_ch3 pc2 (hs)/tim1_ch2 pc1 (hs)/tim1_ch1 pe5/spi_nss pc7 (hs)/spi_miso pc6 (hs)/spi_mosi pc5 (hs)/spi_sck pc4 (hs)/tim1_ch4 pd3 (hs)/tim2_ch2 [adc_etr] pd2 (hs)/tim3_ch1[tim2_ch3] pd1 (hs)/swim pd0 (hs)/tim3_ch2 [tim1_bkin] [clk_cco] pd7/tli pd6/uart3_rx pd5/uart3_tx pd4 (hs)/tim2_ch1 [beep]
pinouts and pin description stm8s207xx, stm8s208xx 28/103 doc id 14733 rev 12 table 5. legend/abbreviations for pinout table type i= input, o = output, s = power supply level input cm = cmos output hs = high sink output speed o1 = slow (up to 2 mhz) o2 = fast (up to 10 mhz) o3 = fast/slow programmability with slow as default state after reset o4 = fast/slow programmability with fast as default state after reset port and control configuration input float = floating, wpu = weak pull-up output t = true open drain, od = open drain, pp = push pull reset state bold x (pin state after inte rnal reset release) unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release. table 6. pin description pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp44 lqfp32 floating wpu ext. interrupt high sink speed od pp 11111nrst i/o x reset 2 2 2 2 2 pa1/oscin i/o x xo1xx port a1 resonator/ crystal in 3 3 3 3 3 pa2/oscout i/o x xx o1xx port a2 resonator/ crystal out 4444 -v ssio_1 s i/o ground 55554v ss s digital ground 6 6 6 6 5 vcap s 1.8 v regulator capacitor 77776v dd s digital power supply 88887v ddio_1 s i/o power supply 9 9 9 - - pa3/tim2_ch3 i/o x xx o1xx port a3 timer 2 - channel3 tim3_ch1 [afr1] 10 10 10 9 - pa4/uart1_rx (1) i/o x xxhso3xx port a4 uart1 receive 11 11 11 10 - pa5/uart1_tx i/o x xxhso3xx port a5 uart1 transmit 12 12 12 11 - pa6/uart1_ck i/o x xxhso3xx port a6 uart1 synchronous clock 13----ph0 i/o x xhso3xx port h0 14----ph1 i/o x xhso3xx port h1 15----ph2 i/o x xo1xx port h2
stm8s207xx, stm8s208xx pinouts and pin description doc id 14733 rev 12 29/103 16----ph3 i/o x xo1xx port h3 17 13 - - - pf7/ain15 i/o x xo1xx port f7 analog input 15 18 14 - - - pf6/ain14 i/o x xo1xx port f6 analog input 14 19 15 - - - pf5/ain13 i/o x xo1xx port f5 analog input 13 20 16 - - 8 pf4/ain12 i/o x xo1xx port f4 analog input 12 21 17 - - - pf3/ain11 i/o x xo1xx port f3 analog input 11 22 18 - - - v ref+ s adc positive reference voltage 23 19 13 12 9 v dda s analog power supply 24 20 14 13 10 v ssa s analog ground 25 21 - - - v ref- s adc negative reference voltage 26 22 - - - pf0/ain10 i/o x xo1xx port f0 analog input 10 27 23 15 14 - pb7/ain7 i/o x xx o1xx port b7 analog input 7 28 24 16 15 - pb6/ain6 i/o x xx o1xx port b6 analog input 6 29 25 17 16 11 pb5/ain5 i/o x xx o1xx port b5 analog input 5 i 2 c_sda [afr6] 30 26 18 17 12 pb4/ain4 i/o x xx o1xx port b4 analog input 4 i 2 c_scl [afr6] 31 27 19 18 13 pb3/ain3 i/o x xx o1xx port b3 analog input 3 tim1_etr [afr5] 32 28 20 19 14 pb2/ain2 i/o x xx o1xx port b2 analog input 2 tim1_ ch3n [afr5] 33 29 21 20 15 pb1/ain1 i/o x xx o1xx port b1 analog input 1 tim1_ ch2n [afr5] 34 30 22 21 16 pb0/ain0 i/o x xx o1xx port b0 analog input 0 tim1_ ch1n [afr5] table 6. pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp44 lqfp32 floating wpu ext. interrupt high sink speed od pp
pinouts and pin description stm8s207xx, stm8s208xx 30/103 doc id 14733 rev 12 35 - - - - ph4/tim1_etr i/o x xo1xx port h4 timer 1 - trigger input 36 - - - - ph5/ tim1_ch3n i/o x xo1xx port h5 timer 1 - inverted channel 3 37 - - - - ph6/ tim1_ch2n i/o x xo1xx port h6 timer 1 - inverted channel 2 38 - - - - ph7/ tim1_ch1n i/o x xo1xx port h7 timer 1 - inverted channel 2 39 31 23 - - pe7/ain8 i/o x xx o1xx port e7 analog input 8 40 32 24 22 - pe6/ain9 i/o x xx o1xx port e6 analog input 9 41 33 25 23 17 pe5/spi_nss i/o x xx o1xx port e5 spi master/slave select 42 - - - - pc0/adc_etr i/o x xx o1xx port c0 adc trigger input 43 34 26 24 18 pc1/tim1_ch1 i/o x xxhso3xx port c1 timer 1 - channel 1 44 35 27 25 19 pc2/tim1_ch2 i/o x xxhso3xx port c2 timer 1- channel 2 45 36 28 26 20 pc3/tim1_ch3 i/o x xxhso3xx port c3 timer 1 - channel 3 46 37 29 - 21 pc4/tim1_ch4 i/o x xxhso3xx port c4 timer 1 - channel 4 47 38 30 27 22 pc5/spi_sck i/o x xxhso3xx port c5 spi clock 48 39 31 28 - v ssio_2 s i/o ground 49 40 32 29 - v ddio_2 s i/o power supply 50 41 33 30 23 pc6/spi_mosi i/o x xxhso3xx port c6 spi master out/ slave in 51 42 34 31 24 pc7/spi_miso i/o x xxhso3xx port c7 spi master in/ slave out 52 43 35 32 - pg0/can_tx (2) i/o x xo1xx port g0 becan transmit 53 44 36 33 - pg1/can_rx (2) i/o x xo1xx port g1 becan receive table 6. pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp44 lqfp32 floating wpu ext. interrupt high sink speed od pp
stm8s207xx, stm8s208xx pinouts and pin description doc id 14733 rev 12 31/103 54 45 - - - pg2 i/o x xo1xx port g2 55 46 - - - pg3 i/o x xo1xx port g3 56 47 - - - pg4 i/o x xo1xx port g4 57 48 - - - pi0 i/o x xo1xx port i0 58----pi1 i/o x xo1xx port i1 59----pi2 i/o x xo1xx port i2 60----pi3 i/o x xo1xx port i3 61----pi4 i/o x xo1xx port i4 62----pi5 i/o x xo1xx port i5 63 49 - - - pg5 i/o x xo1xx port g5 64 50 - - - pg6 i/o x xo1xx port g6 65 51 - - - pg7 i/o x xo1xx port g7 66 52 - - - pe4 i/o x xx o1xx port e4 67 53 37 - - pe3/tim1_bkin i/o x xx o1xx port e3 timer 1 - break input 68 54 38 34 - pe2/i 2 c_sda i/o x xo1t (3) port e2 i 2 c data 69 55 39 35 - pe1/i 2 c_scl i/o x xo1t (3) port e1 i 2 c clock 70 56 40 36 - pe0/clk_cco i/o x xxhso3xx port e0 configurable clock output 71----pi6 i/o x xo1xx port i6 72----pi7 i/o x xo1xx port i7 73 57 41 37 25 pd0/tim3_ch2 i/o x xxhso3xx port d0 timer 3 - channel 2 tim1_bkin [afr3]/ clk_cco [afr2] 74 58 42 38 26 pd1/swim (4) i/o x x xhso4x x port d1 swim data interface 75 59 43 39 27 pd2/tim3_ch1 i/o x xxhso3xx port d2 timer 3 - channel 1 tim2_ch3 [afr1] 76 60 44 40 28 pd3/tim2_ch2 i/o x xxhso3xx port d3 timer 2 - channel 2 adc_etr [afr0] 77 61 45 41 29 pd4/tim2_ch1/b eep i/o x xxhso3xx port d4 timer 2 - channel 1 beep output [afr7] 78 62 46 42 30 pd5/ uart3_tx i/o x xx o1xx port d5 uart3 data transmit table 6. pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp44 lqfp32 floating wpu ext. interrupt high sink speed od pp
pinouts and pin description stm8s207xx, stm8s208xx 32/103 doc id 14733 rev 12 5.2 alternate function remapping as shown in the rightmost column of the pin description table, some alternate functions can be remapped at different i/o ports by programming one of eight afr (alternate function remap) option bits. refer to section 8: option bytes on page 46 . when the remapping option is active, the default alternate function is no longer available. to use an alternate function, the corresponding pe ripheral must be enabled in the peripheral registers. alternate function remapping d oes not effect gpio capabilitie s of the i/o ports (see the gpio section of the family reference manual, rm0016). 79 63 47 43 31 pd6/ uart3_rx (1) i/o x xx o1xx port d6 uart3 data receive 80 64 48 44 32 pd7/tli i/o x xx o1xx port d7 to p l eve l interrupt tim1_ch4 [afr4] (5) 1. the default state of uart1_rx and uart3_rx pins is cont rolled by the rom bootloader. t hese pins are pulled up as part of the bootloader activation process and returned to the floating state before a return from the bootloader. 2. the becan interface is avai lable on stm8s208xx devices only 3. in the open-drain output column , ?t? defines a true open-drain i/o (p-buffer, weak pull-up, and protection diode to v dd are not implemented). 4. the pd1 pin is in input pull-up during the re set phase and after the internal reset release. 5. available in 44-pin package only. on other packages, the afr4 bit is reserved and must be kept at 0. table 6. pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp44 lqfp32 floating wpu ext. interrupt high sink speed od pp
stm8s207xx, stm8s208xx memory and register map doc id 14733 rev 12 33/103 6 memory and register map 6.1 memory map figure 8. memory map gpio and peripher al registers 0x00 0000 reserved flash program memory (64 to 128 kbytes) 32 interrupt vectors 0x 00 4000 0x 00 47ff ram 0x 00 17ff (up to 6 kbytes) 1024 bytes stack up to 2 kbytes data eeprom 0x 00 4800 0x 00 487f option bytes 0x 00 5000 0x 00 57ff 0x 00 5800 0x 00 7fff 0x 00 8000 0x 02 7fff (see ta bl e 8 and ta bl e 9 ) 0x 00 1800 0x 00 3fff 0x 00 4900 0x 00 4fff 2 kbytes boot rom 0x 00 6000 0x 00 67ff 0x 00 6800 0x 00 7eff 0x 00 8080 0x 00 807f cpu/swim/debug/itc (see table 10 ) registers 0x 00 7f00 0x 00 5fff reserved reserved reserved
memory and register map stm8s207xx, stm8s208xx 34/103 doc id 14733 rev 12 ta bl e 7 lists the boundary addresses for each memory size. the top of the stack is at the ram end address in each case. 6.2 register map table 7. flash, data eeprom and ram boundary addresses memory area size (bytes) start address end address flash program memory 128 k 0x00 8000 0x02 7fff 64 k 0x00 8000 0x01 7fff 32 k 0x00 8000 0x00 ffff ram 6 k 0x00 0000 0x00 17ff 4 k 0x00 0000 0x00 1000 2 k 0x00 0000 0x00 07ff data eeprom 2048 0x00 4000 0x00 47ff 1536 0x00 4000 0x00 45ff 1024 0x00 4000 0x00 43ff table 8. i/o port hardware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data output latch register 0x00 0x00 5001 pa_idr port a input pin value register 0x00 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x00 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output latch register 0x00 0x00 5006 pb_idr port b input pin value register 0x00 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 0x00 500a port c pc_odr port c data output latch register 0x00 0x00 500b pb_idr port c input pin value register 0x00 0x00 500c pc_ddr port c data direction register 0x00 0x00 500d pc_cr1 port c control register 1 0x00 0x00 500e pc_cr2 port c control register 2 0x00
stm8s207xx, stm8s208xx memory and register map doc id 14733 rev 12 35/103 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0x00 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control register 1 0x02 0x00 5013 pd_cr2 port d control register 2 0x00 0x00 5014 port e pe_odr port e data output latch register 0x00 0x00 5015 pe_idr port e input pin value register 0x00 0x00 5016 pe_ddr port e data direction register 0x00 0x00 5017 pe_cr1 port e control register 1 0x00 0x00 5018 pe_cr2 port e control register 2 0x00 0x00 5019 port f pf_odr port f data output latch register 0x00 0x00 501a pf_idr port f input pin value register 0x00 0x00 501b pf_ddr port f data direction register 0x00 0x00 501c pf_cr1 port f control register 1 0x00 0x00 501d pf_cr2 port f control register 2 0x00 0x00 501e port g pg_odr port g data output latch register 0x00 0x00 501f pg_idr port g input pin value register 0x00 0x00 5020 pg_ddr port g data direction register 0x00 0x00 5021 pg_cr1 port g control register 1 0x00 0x00 5022 pg_cr2 port g control register 2 0x00 0x00 5023 port h ph_odr port h data output latch register 0x00 0x00 5024 ph_idr port h input pin value register 0x00 0x00 5025 ph_ddr port h data direction register 0x00 0x00 5026 ph_cr1 port h control register 1 0x00 0x00 5027 ph_cr2 port h control register 2 0x00 0x00 5028 port i pi_odr port i data output latch register 0x00 0x00 5029 pi_idr port i input pin value register 0x00 0x00 502a pi_ddr port i data direction register 0x00 0x00 502b pi_cr1 port i control register 1 0x00 0x00 502c pi_cr2 port i control register 2 0x00 table 8. i/o port hardware register map (continued) address block register label register name reset status
memory and register map stm8s207xx, stm8s208xx 36/103 doc id 14733 rev 12 table 9. general hardware register map address block register label register name reset status 0x00 5050 to 0x00 5059 reserved area (10 bytes) 0x00 505a flash flash_cr1 flash control register 1 0x00 0x00 505b flash_cr2 flash control register 2 0x00 0x00 505c flash_ncr2 flash complementary control register 2 0xff 0x00 505d flash _fpr flash protection register 0x00 0x00 505e flash _nfpr flash complementary protection register 0xff 0x00 505f flash _iapsr flash in-application programming status register 0x00 0x00 5060 to 0x00 5061 reserved area (2 bytes) 0x00 5062 flash flash _pukr flash program memory unprotection register 0x00 0x00 5063 reserved area (1 byte) 0x00 5064 flash flash _dukr data eeprom unprotection register 0x00 0x00 5065 to 0x00 509f reserved area (59 bytes) 0x00 50a0 itc exti_cr1 external interrupt control register 1 0x00 0x00 50a1 exti_cr2 external interrupt control register 2 0x00 0x00 50a2 to 0x00 50b2 reserved area (17 bytes) 0x00 50b3 rst rst_sr reset status register 0xxx (1) 0x00 50b4 to 0x00 50bf reserved area (12 bytes) 0x00 50c0 clk clk_ickr internal clock control register 0x01 0x00 50c1 clk_eckr external clock control register 0x00 0x00 50c2 reserved area (1 byte) 0x00 50c3 clk clk_cmsr clock master status register 0xe1 0x00 50c4 clk_swr clock master switch register 0xe1 0x00 50c5 clk_swcr clock switch control register 0xxx 0x00 50c6 clk_ckdivr clock divider register 0x18 0x00 50c7 clk_pckenr1 peripheral clock gating register 1 0xff 0x00 50c8 clk_cssr clock security system register 0x00 0x00 50c9 clk_ccor configurable clock control register 0x00 0x00 50ca clk_pckenr2 peripheral clock gating register 2 0xff 0x00 50cb clk_canccr can clock control register 0x00
stm8s207xx, stm8s208xx memory and register map doc id 14733 rev 12 37/103 0x00 50cc clk clk_hsitrimr hsi clock calibration trimming register 0x00 0x00 50cd clk_swimccr swim clock control register 0bxxxx xxx0 0x00 50ce to 0x00 50d0 reserved area (3 bytes) 0x00 50d1 wwdg wwdg_cr wwdg control register 0x7f 0x00 50d2 wwdg_wr wwdr window register 0x7f 0x00 50d3 to 0x00 50df reserved area (13 bytes) 0x00 50e0 iwdg iwdg_kr iwdg key register 0xxx (2) 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 bytes) 0x00 50f0 awu awu_csr1 awu control/status register 1 0x00 0x00 50f1 awu_apr awu asynchronous prescaler buffer register 0x3f 0x00 50f2 awu_tbr awu timebase selection register 0x00 0x00 50f3 beep beep_csr beep cont rol/status register 0x1f 0x00 50f4 to 0x00 50ff reserved area (12 bytes) 0x00 5200 spi spi_cr1 spi control register 1 0x00 0x00 5201 spi_cr2 spi control register 2 0x00 0x00 5202 spi_icr spi interrupt control register 0x00 0x00 5203 spi_sr spi status register 0x02 0x00 5204 spi_dr spi data register 0x00 0x00 5205 spi_crcpr spi crc polynomial register 0x07 0x00 5206 spi_rxcrcr spi rx crc register 0xff 0x00 5207 spi_txcrcr spi tx crc register 0xff 0x00 5208 to 0x00 520f reserved area (8 bytes) 0x00 5210 i 2 c i2c_cr1 i 2 c control register 1 0x00 0x00 5211 i2c_cr2 i 2 c control register 2 0x00 0x00 5212 i2c_freqr i 2 c frequency register 0x00 0x00 5213 i2c_oarl i 2 c own address register low 0x00 0x00 5214 i2c_oarh i 2 c own address register high 0x00 0x00 5215 reserved table 9. general hardware register map (continued) address block register label register name reset status
memory and register map stm8s207xx, stm8s208xx 38/103 doc id 14733 rev 12 0x00 5216 i 2 c i2c_dr i 2 c data register 0x00 0x00 5217 i2c_sr1 i 2 c status register 1 0x00 0x00 5218 i2c_sr2 i 2 c status register 2 0x00 0x00 5219 i2c_sr3 i 2 c status register 3 0x00 0x00 521a i2c_itr i 2 c interrupt control register 0x00 0x00 521b i2c_ccrl i 2 c clock control register low 0x00 0x00 521c i2c_ccrh i 2 c clock control register high 0x00 0x00 521d i2c_triser i 2 c trise register 0x02 0x00 521e to 0x00 522f reserved area (18 bytes) 0x00 5230 uart1 uart1_sr uart1 status register 0xc0 0x00 5231 uart1_dr uart1 data register 0xxx 0x00 5232 uart1_brr1 uart1 baud rate register 1 0x00 0x00 5233 uart1_brr2 uart1 baud rate register 2 0x00 0x00 5234 uart1_cr1 uart1 control register 1 0x00 0x00 5235 uart1_cr2 uart1 control register 2 0x00 0x00 5236 uart1_cr3 uart1 control register 3 0x00 0x00 5237 uart1_cr4 uart1 control register 4 0x00 0x00 5238 uart1_cr5 uart1 control register 5 0x00 0x00 5239 uart1_gtr uart1 guard time register 0x00 0x00 523a uart1_pscr uart1 prescaler register 0x00 0x00 523b to 0x00 523f reserved area (5 bytes) 0x00 5240 uart3 uart3_sr uart3 status register c0h 0x00 5241 uart3_dr uart3 data register 0xxx 0x00 5242 uart3_brr1 uart3 baud rate register 1 0x00 0x00 5243 uart3_brr2 uart3 baud rate register 2 0x00 0x00 5244 uart3_cr1 uart3 control register 1 0x00 0x00 5245 uart3_cr2 uart3 control register 2 0x00 0x00 5246 uart3_cr3 uart3 control register 3 0x00 0x00 5247 uart3_cr4 uart3 control register 4 0x00 0x00 5248 reserved 0x00 5249 uart3_cr6 uart3 control register 6 0x00 0x00 524a to 0x00 524f reserved area (6 bytes) table 9. general hardware register map (continued) address block register label register name reset status
stm8s207xx, stm8s208xx memory and register map doc id 14733 rev 12 39/103 0x00 5250 tim1 tim1_cr1 tim1 control register 1 0x00 0x00 5251 tim1_cr2 tim1 control register 2 0x00 0x00 5252 tim1_smcr tim1 slave mode control register 0x00 0x00 5253 tim1_etr tim1 external trigger register 0x00 0x00 5254 tim1_ier tim1 interrupt enable register 0x00 0x00 5255 tim1_sr1 tim1 status register 1 0x00 0x00 5256 tim1_sr2 tim1 status register 2 0x00 0x00 5257 tim1_egr tim1 event generation register 0x00 0x00 5258 tim1_ccmr1 tim1 capture/compare mode register 1 0x00 0x00 5259 tim1_ccmr2 tim1 capture/compare mode register 2 0x00 0x00 525a tim1_ccmr3 tim1 capture/compare mode register 3 0x00 0x00 525b tim1_ccmr4 tim1 capture/compare mode register 4 0x00 0x00 525c tim1_ccer1 tim1 capture/compare enable register 1 0x00 0x00 525d tim1_ccer2 tim1 capture/compare enable register 2 0x00 0x00 525e tim1_cntrh tim1 counter high 0x00 0x00 525f tim1_cntrl tim1 counter low 0x00 0x00 5260 tim1_pscrh tim1 prescaler register high 0x00 0x00 5261 tim1_pscrl tim1 prescaler register low 0x00 0x00 5262 tim1_arrh tim1 aut o-reload register high 0xff 0x00 5263 tim1_arrl tim1 auto-reload register low 0xff 0x00 5264 tim1_rcr tim1 repetition counter register 0x00 0x00 5265 tim1_ccr1h tim1 captur e/compare register 1 high 0x00 0x00 5266 tim1_ccr1l tim1 capture/compare register 1 low 0x00 0x00 5267 tim1_ccr2h tim1 captur e/compare register 2 high 0x00 0x00 5268 tim1_ccr2l tim1 capture/compare register 2 low 0x00 0x00 5269 tim1_ccr3h tim1 captur e/compare register 3 high 0x00 0x00 526a tim1_ccr3l tim1 capture/compare register 3 low 0x00 0x00 526b tim1_ccr4h tim1 captur e/compare register 4 high 0x00 0x00 526c tim1_ccr4l tim1 capture/compare register 4 low 0x00 0x00 526d tim1_bkr tim1 break register 0x00 0x00 526e tim1_dtr tim1 dead-time register 0x00 0x00 526f tim1_oisr tim1 output idle state register 0x00 0x00 5270 to 0x00 52ff reserved area (147 bytes) table 9. general hardware register map (continued) address block register label register name reset status
memory and register map stm8s207xx, stm8s208xx 40/103 doc id 14733 rev 12 0x00 5300 tim2 tim2_cr1 tim2 control register 1 0x00 0x00 5301 tim2_ier tim2 interrupt enable register 0x00 0x00 5302 tim2_sr1 tim2 status register 1 0x00 0x00 5303 tim2_sr2 tim2 status register 2 0x00 0x00 5304 tim2_egr tim2 event generation register 0x00 0x00 5305 tim2_ccmr1 tim2 capt ure/compare mode register 1 0x00 0x00 5306 tim2_ccmr2 tim2 capt ure/compare mode register 2 0x00 0x00 5307 tim2_ccmr3 tim2 capt ure/compare mode register 3 0x00 0x00 5308 tim2_ccer1 tim2 capture/compare enable register 1 0x00 0x00 5309 tim2_ccer2 tim2 capture/compare enable register 2 0x00 0x00 530a tim2_cntrh tim2 counter high 0x00 0x00 530b tim2_cntrl tim2 counter low 0x00 00 530c0x tim2_pscr tim2 prescaler register 0x00 0x00 530d tim2_arrh tim2 auto -reload register high 0xff 0x00 530e tim2_arrl tim2 auto-reload register low 0xff 0x00 530f tim2_ccr1h tim2 captur e/compare register 1 high 0x00 0x00 5310 tim2_ccr1l tim2 capture/compare register 1 low 0x00 0x00 5311 tim2_ccr2h tim2 capt ure/compare reg. 2 high 0x00 0x00 5312 tim2_ccr2l tim2 capture/compare register 2 low 0x00 0x00 5313 tim2_ccr3h tim2 captur e/compare register 3 high 0x00 0x00 5314 tim2_ccr3l tim2 capture/compare register 3 low 0x00 0x00 5315 to 0x00 531f reserved area (11 bytes) 0x00 5320 tim3 tim3_cr1 tim3 control register 1 0x00 0x00 5321 tim3_ier tim3 interrupt enable register 0x00 0x00 5322 tim3_sr1 tim3 status register 1 0x00 0x00 5323 tim3_sr2 tim3 status register 2 0x00 0x00 5324 tim3_egr tim3 event generation register 0x00 0x00 5325 tim3_ccmr1 tim3 capture/compare mode register 1 0x00 0x00 5326 tim3_ccmr2 tim3 capture/compare mode register 2 0x00 0x00 5327 tim3_ccer1 tim3 capture/compare enable register 1 0x00 0x00 5328 tim3_cntrh tim3 counter high 0x00 0x00 5329 tim3_cntrl tim3 counter low 0x00 0x00 532a tim3_pscr tim3 prescaler register 0x00 table 9. general hardware register map (continued) address block register label register name reset status
stm8s207xx, stm8s208xx memory and register map doc id 14733 rev 12 41/103 0x00 532b tim3 tim3_arrh tim3 auto-reload register high 0xff 0x00 532c tim3_arrl tim3 auto-reload register low 0xff 0x00 532d tim3_ccr1h tim3 captur e/compare register 1 high 0x00 0x00 532e tim3_ccr1l tim3 capture/compare register 1 low 0x00 0x00 532f tim3_ccr2h tim3 captur e/compare register 2 high 0x00 0x00 5330 tim3_ccr2l tim3 capture/compare register 2 low 0x00 0x00 5331 to 0x00 533f reserved area (15 bytes) 0x00 5340 tim4 tim4_cr1 tim4 control register 1 0x00 0x00 5341 tim4_ier tim4 interrupt enable register 0x00 0x00 5342 tim4_sr tim4 status register 0x00 0x00 5343 tim4_egr tim4 event generation register 0x00 0x00 5344 tim4_cntr tim4 counter 0x00 0x00 5345 tim4_pscr tim4 prescaler register 0x00 0x00 5346 tim4_arr tim4 auto-reload register 0xff 0x00 5347 to 0x00 53ff reserved area (185 bytes) 0x00 5400 adc2 adc _csr adc control/status register 0x00 0x00 5401 adc_cr1 adc configuration register 1 0x00 0x00 5402 adc_cr2 adc configuration register 2 0x00 0x00 5403 adc_cr3 adc configuration register 3 0x00 0x00 5404 adc_drh adc data register high 0xxx 0x00 5405 adc_drl adc data register low 0xxx 0x00 5406 adc_tdrh adc schmitt trigger disable register high 0x00 0x00 5407 adc_tdrl adc schmitt trigger disable register low 0x00 0x00 5408 to 0x00 541f reserved area (24 bytes) 0x00 5420 becan can_mcr can master control register 0x02 0x00 5421 can_msr can master status register 0x02 0x00 5422 can_tsr can transmit status register 0x00 0x00 5423 can_tpr can transmit priority register 0x0c 0x00 5424 can_rfr can receive fifo register 0x00 0x00 5425 can_ier can interrupt enable register 0x00 0x00 5426 can_dgr can diagnosis register 0x0c 0x00 5427 can_fpsr can page selection register 0x00 table 9. general hardware register map (continued) address block register label register name reset status
memory and register map stm8s207xx, stm8s208xx 42/103 doc id 14733 rev 12 0x00 5428 becan can_p0 can paged register 0 0xxx (3) 0x00 5429 can_p1 can paged register 1 0xxx (3) 0x00 542a can_p2 can paged register 2 0xxx (3) 0x00 542b can_p3 can paged register 3 0xxx (3) 0x00 542c can_p4 can paged register 4 0xxx (3) 0x00 542d can_p5 can paged register 5 0xxx (3) 0x00 542e can_p6 can paged register 6 0xxx (3) 0x00 542f can_p7 can paged register 7 0xxx (3) 0x00 5430 can_p8 can paged register 8 0xxx (3) 0x00 5431 can_p9 can paged register 9 0xxx (3) 0x00 5432 can_pa can paged register a 0xxx (3) 0x00 5433 can_pb can paged register b 0xxx (3) 0x00 5434 can_pc can paged register c 0xxx (3) 0x00 5435 can_pd can paged register d 0xxx (3) 0x00 5436 can_pe can paged register e 0xxx (3) 0x00 5437 can_pf can paged register f 0xxx (3) 0x00 5438 to 0x00 57ff reserved area (968 bytes) 1. depends on the previous reset source. 2. write only register. 3. if the bootloader is enabled, it is initialized to 0x00. table 9. general hardware register map (continued) address block register label register name reset status
stm8s207xx, stm8s208xx memory and register map doc id 14733 rev 12 43/103 table 10. cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu (1) a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x00 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x17 (2) 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a ccr condition code register 0x28 0x00 7f0b to 0x00 7f5f reserved area (85 bytes) 0x00 7f60 cpu cfg_gcr global co nfiguration register 0x00 0x00 7f70 itc itc_spr1 interrupt software priority register 1 0xff 0x00 7f71 itc_spr2 interrupt softwa re priority register 2 0xff 0x00 7f72 itc_spr3 interrupt softwa re priority register 3 0xff 0x00 7f73 itc_spr4 interrupt softwa re priority register 4 0xff 0x00 7f74 itc_spr5 interrupt softwa re priority register 5 0xff 0x00 7f75 itc_spr6 interrupt softwa re priority register 6 0xff 0x00 7f76 itc_spr7 interrupt softwa re priority register 7 0xff 0x00 7f77 itc_spr8 interrupt softwa re priority register 8 0xff 0x00 7f78 to 0x00 7f79 reserved area (2 bytes) 0x00 7f80 swim swim_csr swim control status register 0x00 0x00 7f81 to 0x00 7f8f reserved area (15 bytes) 0x00 7f90 dm dm_bk1re dm breakpoint 1 register extended byte 0xff 0x00 7f91 dm_bk1rh dm breakpoint 1 register high byte 0xff 0x00 7f92 dm_bk1rl dm breakpoint 1 register low byte 0xff 0x00 7f93 dm_bk2re dm breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh dm breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl dm breakpoint 2 register low byte 0xff 0x00 7f96 dm_cr1 dm debug module control register 1 0x00 0x00 7f97 dm_cr2 dm debug module control register 2 0x00
memory and register map stm8s207xx, stm8s208xx 44/103 doc id 14733 rev 12 0x00 7f98 dm dm_csr1 dm debug module control/status register 1 0x10 0x00 7f99 dm_csr2 dm debug module control/status register 2 0x00 0x00 7f9a dm_enfctr dm enable function register 0xff 0x00 7f9b to 0x00 7f9f reserved area (5 bytes) 1. accessible by debug module only 2. product dependent value, see figure 8: memory map . table 10. cpu/swim/debug module/interrupt controller registers (continued) address block register label register name reset status
stm8s207xx, stm8s208xx interrupt vector mapping doc id 14733 rev 12 45/103 7 interrupt vector mapping table 11. interrupt mapping irq no. source block description wakeup from halt mode wakeup from active-h alt mode vector address reset reset yes yes 0x00 8000 trap software interrupt - - 0x00 8004 0 tli external top level interrupt - - 0x00 8008 1 awu auto wake up from halt - yes 0x00 800c 2 clk clock controller - - 0x00 8010 3 exti0 port a external interrupts yes (1) ye s (1) 0x00 8014 4 exti1 port b external interrupts yes yes 0x00 8018 5 exti2 port c external interrupts yes yes 0x00 801c 6 exti3 port d external interrupts yes yes 0x00 8020 7 exti4 port e external interrupts yes yes 0x00 8024 8 becan becan rx interrupt yes yes 0x00 8028 9 becan becan tx/er/sc interrupt - - 0x00 802c 10 spi end of transfer yes yes 0x00 8030 11 tim1 tim1 update/overflow/underflow/ trigger/break - - 0x00 8034 12 tim1 tim1 capture/compare - - 0x00 8038 13 tim2 tim2 update /overflow - - 0x00 803c 14 tim2 tim2 capture/compare - - 0x00 8040 15 tim3 update/overflow - - 0x00 8044 16 tim3 capture/compare - - 0x00 8048 17 uart1 tx complete - - 0x00 804c 18 uart1 receive register data full - - 0x00 8050 19 i 2 ci 2 c interrupt yes yes 0x00 8054 20 uart3 tx complete - - 0x00 8058 21 uart3 receive register data full - - 0x00 805c 22 adc2 adc2 end of conversion - - 0x00 8060 23 tim4 tim4 update/overflow - - 0x00 8064 24 flash eop/wr_pg_dis - - 0x00 8068 reserved 0x00 806c to 0x00 807c 1. except pa1
option bytes stm8s207xx, stm8s208xx 46/103 doc id 14733 rev 12 8 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated block of the memory. except for the rop (read-out protection) byte, each option byte has to be stored twice, in a regular form (optx) and a complemented one (noptx) for redundancy. option bytes can be modified in icp mode (v ia swim) by accessing the eeprom address shown in ta b l e 12: option bytes below. option bytes can also be modified ?on the fly? by the application in iap mode, except the rop option that can only be modified in icp mode (via swim). refer to the stm8s flash programming manual (pm0051) and stm8 swim communication protocol and debug module user manual (um0470) for information on swim programming procedures. table 12. option bytes addr. option name option byte no. option bits factory default setting 7654 3 2 1 0 4800h read-out protection (rop) opt0 rop[7:0] 00h 4801h user boot code(ubc) opt1 ubc[7:0] 00h 4802h nopt1 nubc[7:0] ffh 4803h alternate function remapping (afr) opt2 afr7 afr6 afr5 afr4 afr3 afr2 afr1 afr0 00h 4804h nopt2 nafr7 nafr6 nafr5 nafr4 nafr3 nafr2 nafr1 nafr0 ffh 4805h watchdog option opt3 reserved lsi _en iwdg _hw wwdg _hw wwdg _halt 00h 4806h nopt3 reserved nlsi _en niwdg _hw nwwdg _hw nwwdg _halt ffh 4807h clock option opt4 reserved ext clk ckawu sel prs c1 prs c0 00h 4808h nopt4 reserved next clk nckawus el npr sc1 npr sc0 ffh 4809h hse clock startup opt5 hsecnt[7:0] 00h 480ah nopt5 nhsecnt[7:0] ffh 480bh reserved opt6 reserved 00h 480ch nopt6 reserved ffh 480dh flash wait states opt7 reserved wait state 00h 480eh nopt7 reserved nwait state ffh 487eh bootloader optbl bl[7:0] 00h 487fh noptbl nbl[7:0] ffh
stm8s207xx, stm8s208xx option bytes doc id 14733 rev 12 47/103 table 13. option byte description option byte no. description opt0 rop[7:0] memory readout protection (rop) 0xaa: enable readout protection (write access via swim protocol) note: refer to the family refer ence manual (rm0016) section on flash/eeprom memory readout protection for details. opt1 ubc[7:0] user boot code area 0x00: no ubc, no write-protection 0x01: pages 0 to 1 defined as ubc, memory write-protected 0x02: pages 0 to 3 defined as ubc, memory write-protected 0x03: pages 0 to 4 defined as ubc, memory write-protected ... 0xfe: pages 0 to 255 defined as ubc, memory write-protected 0xff: reserved note: refer to the family refer ence manual (rm0016) section on flash/eeprom write protection for more details. opt2 afr7 alternate function remapping option 7 0: port d4 alternate function = tim2_ch1 1: port d4 alternate function = beep afr6 alternate function remapping option 6 0: port b5 alternate function = ai n5, port b4 alternate function = ain4 1: port b5 alternate function = i 2 c_sda, port b4 alternate function = i 2 c_scl afr5 alternate function remapping option 5 0: port b3 alternate function = ai n3, port b2 alternate function = ain2, port b1 alternate function = ain1, port b0 alternate function = ain0 1: port b3 alternate function = ti m1_etr, port b2 alternate function = tim1_ch3n, port b1 alternate functi on = tim1_ch2n, port b0 alternate function = tim1_ch1n afr4 alternate function remapping option 4 0: port d7 alternate function = tli 1: port d7 alternate function = tim1_ch4 afr3 alternate function remapping option 3 0: port d0 alternate function = tim3_ch2 1: port d0 alternate function = tim1_bkin afr2 alternate function remapping option 2 0: port d0 alternate function = tim3_ch2 1: port d0 alternate function = clk_cco note: afr2 option has priority over afr3 if both are activated afr1 alternate function remapping option 1 0: port a3 alternate function = ti m2_ch3, port d2 alternate function tim3_ch1 1: port a3 alternate function = ti m3_ch1, port d2 alternate function tim2_ch3 afr0 alternate function remapping option 0 0: port d3 alternate function = tim2_ch2 1: port d3 alternate function = adc_etr
option bytes stm8s207xx, stm8s208xx 48/103 doc id 14733 rev 12 opt3 lsi_en: low speed internal clock enable 0: lsi clock is not available as cpu clock source 1: lsi clock is available as cpu clock source iwdg_hw: independent watchdog 0: iwdg independent watchdog activated by software 1: iwdg independent watchdog activated by hardware wwdg_hw: window watchdog activation 0: wwdg window watchdog activated by software 1: wwdg window watchdog activated by hardware wwdg_halt: window watchdog reset on halt 0: no reset generated on halt if wwdg active 1: reset generated on halt if wwdg active opt4 extclk: external clock selection 0: external crystal c onnected to oscin/oscout 1: external clock signal on oscin ckawusel: auto wakeup unit/clock 0: lsi clock source selected for awu 1: hse clock with prescaler selected as clock source for for awu prsc[1:0] awu clock prescaler 00: 24 mhz to 128 khz prescaler 01: 16 mhz to 128 khz prescaler 10: 8 mhz to 128 khz prescaler 11: 4 mhz to 128 khz prescaler opt5 hsecnt[7:0]: hse crystal oscillator stabilization time this configures the stabilisation time. 0x00: 2048 hse cycles 0xb4: 128 hse cycles 0xd2: 8 hse cycles 0xe1: 0.5 hse cycles opt6 reserved opt7 waitstate wait state configuration this option configures the number of wait states inserted when reading from the flash/data eeprom memory. 1 wait state is required if f cpu > 16 mhz. 0: no wait state 1: 1 wait state table 13. option byte description (continued) option byte no. description
stm8s207xx, stm8s208xx option bytes doc id 14733 rev 12 49/103 optbl bl[7:0] bootloader option byte for stm8s products, this option is checked by the boot rom code after reset. depending on the content of addresses 0x487e, 0x487f, and 0x8000 (reset vector), the cpu jumps to the bootloader or to the reset vector. refer to the um0560 (stm8l/s bootloader manual) for more details. for stm8l products, the bootloader option bytes are on addresses 0xxxxx and 0xxxxx+1 (2 bytes) . these option bytes control whether the bootloader is active or not. for more details, refer to the um0560 (stm8l/s bootloader manual) for more details. table 13. option byte description (continued) option byte no. description
unique id stm8s207xx, stm8s208xx 50/103 doc id 14733 rev 12 9 unique id the devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. the 96 bits of the identifier can never be altered by the user. the unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. the unique device identifier is ideally suited: for use as serial numbers for use as security keys to increase the code security in the program memory while using and combining this unique id with software crytograhic primitives and protocols before programming the internal memory. to activate secure boot processes table 14. unique id registers (96 bits) address content description unique id bits 7654 3 2 1 0 0x48cd x co-ordinate on the wafer u_id[7:0] 0x48ce u_id[15:8] 0x48cf y co-ordinate on the wafer u_id[23:16] 0x48d0 u_id[31:24] 0x48d1 wafer number u_id[39:32] 0x48d2 lot number u_id[47:40] 0x48d3 u_id[55:48] 0x48d4 u_id[63:56] 0x48d5 u_id[71:64] 0x48d6 u_id[79:72] 0x48d7 u_id[87:80] 0x48d8 u_id[95:88]
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 51/103 10 electrical characteristics 10.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 10.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at t a = 25 c and t a = t amax (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 10.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 5 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ) . 10.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 typical current consumption for typical current consumption measurements, v dd , v ddio and v dda are connected together in the configuration shown in figure 9 . figure 9. supply current measurement conditions v dd v dda v ddio v ss v ssa v ssio a 5 v or 3.3 v
electrical characteristics stm8s207xx, stm8s208xx 52/103 doc id 14733 rev 12 10.1.5 pin loading conditions 10.1.6 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 10 . figure 10. pin loading conditions 10.1.7 pin input voltage the input voltage measurement on a pin of the device is described in figure 11 . figure 11. pin input voltage 50 pf stm8 pin v in stm8 pin
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 53/103 10.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 15. voltage characteristics symbol ratings min max unit v ddx - v ss supply voltage (including v dda and v ddio ) (1) 1. all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external power supply -0.3 6.5 v v in input voltage on true open drain pins (pe1, pe2) (2) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics stm8s207xx, stm8s208xx 54/103 doc id 14733 rev 12 table 16. current characteristics symbol ratings max. (1) 1. data based on characterization results, not tested in production. unit i vdd total current into v dd power lines (source) (2) 2. all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external supply. 60 ma i vss total current out of v ss ground lines (sink) (2) 60 i io output current sunk by any i/o and control pin 20 output current source by any i/os and control pin 20 i io total output current sourced (sum of all i/o and control pins) for devices with two v ddio pins (3) 3. i/o pins used simultaneously for high current so urce/sink must be uniformly spaced around the package between the v ddio /v ssio pins. 200 total output current sourced (sum of all i/o and control pins) for devices with one v ddio pin (3) 100 total output current sunk (sum of all i/o and control pins) for devices with two v ssio pins (3) 160 total output current sunk (sum of all i/o and control pins) for devices with one v ssio pin (3) 80 i inj(pin) (4)(5) 4. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 55/103 10.3 operating conditions the device must be used in operating cond itions that respect the parameters in ta b l e 18 . in addition, full account must be taken of all physical capacitor characteristics and tolerances. table 18. general operating conditions symbol parameter conditions min max unit f cpu internal cpu clock frequency t a 105 c 0 24 mhz 0 16 mhz v dd/ v dd_io standard operating voltage 2.95 5.5 v v cap (1) 1. care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, dc bias and frequency in addi tion to other factors. the parameter maximum value must be respected for the full application range. c ext : capacitance of external capacitor 470 3300 nf esr of external capacitor at 1 mhz (2) 2. this frequency of 1 mhz as a condition for v cap parameters is given by des ign of internal regulator. -0.3 esl of external capacitor - 15 nh p d (3) 3. to calculate p dmax (t a ), use the formula p dmax = (t jmax - t a )/ ja (see section 11.2: thermal characteristics on page 95 ) with the value for t jmax given in table 18 above and the value for ja given in table 57: thermal characteristics . power dissipation at t a = 85 c for suffix 6 or t a = 125 c for suffix 3 44, 48, 64, and 80-pin devices, with output on 8 standard ports, 2 high sink ports and 2 open drain ports simultaneously (4) 4. refer to section 11.2: thermal characteristics on page 95 for the calculation method. 443 mw 32-pin package, with output on 8 standard ports and 2 high sink ports simultaneously (4) 360 t a ambient temperature for 6 suffix version maximum power dissipation -40 85 c ambient temperature for 3 suffix version maximum power dissipation -40 125 t j junction temperature range 6 suffix version -40 105 3 suffix version -40 130 (5) 5. t jmax is given by the test limit. above this value the product behavior is not guaranteed.
electrical characteristics stm8s207xx, stm8s208xx 56/103 doc id 14733 rev 12 figure 12. f cpumax versus v dd 10.3.1 vcap external capacitor stabilization for the ma in regulator is achieved connecting an external capacitor c ext to the v cap pin. c ext is specified in ta b l e 18 . care should be taken to limit the series inductance to less than 15 nh. figure 13. external capacitor c ext 1. legend: esr is the equivalent series resi stance and esl is the equivalent inductance. table 19. operating conditions at power-up/power-down symbol parameter conditions min typ max unit t vdd v dd rise time rate 2 (1) 1. guaranteed by design, not tested in production. s/v v dd fall time rate 2 (1) t temp reset release delay v dd rising 1.7 (1) ms v it+ power-on reset threshold 2.65 2.8 2.95 v v it- brown-out reset threshold 2.58 2.73 2.88 v v hys(bor) brown-out reset hysteresis 70 mv f cpu [mhz] supply voltage [v] 24 12 8 4 0 2.95 4.0 5.0 functionality functionality guaranteed @ t a -40 to 125 c not guaranteed in this area 16 5.5 functionality guaranteed @ t a -40 to 105 c c rleak esr esl
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 57/103 10.3.2 supply current characteristics the current consumption is measured as described in figure 9 on page 51 . total current consumption in run mode the mcu is placed under the following conditions: all i/o pins in input mode with a static value at v dd or v ss (no load) all peripherals are disabled (clock stopped by peripheral clock gating registers) except if explicitly mentioned. when the mcu is clocked at 24 mhz, t a 105 c and the waitstate option bit is set. subject to general operating conditions for v dd and t a . table 20. total current consumption with code execution in run mode at v dd = 5 v symbol parameter conditions typ max unit i dd(run) supply current in run mode, code executed from ram f cpu = f master = 24 mhz, t a 105 c hse crystal osc. (24 mhz) 4.4 ma hse user ext. clock (24 mhz) 3.7 7.3 (1) f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 3.3 hse user ext. clock (16 mhz) 2.7 5.8 hsi rc osc. (16 mhz) 2.5 3.4 f cpu = f master /128 = 125 khz hse user ext. clock (16 mhz) 1.2 4.1 (1) hsi rc osc. (16 mhz) 1.0 1.3 (1) f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.55 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.45 supply current in run mode, code executed from flash f cpu = f master = 24 mhz, t a 105 c hse crystal osc. (24 mhz) 11.4 hse user ext. clock (24 mhz) 10.8 18 (1) f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 9.0 hse user ext. clock (16 mhz) 8.2 15.2 (1) hsi rc osc.(16 mhz) 8.1 13.2 (1) f cpu = f master = 2 mhz. hsi rc osc. (16 mhz/8) (2) 1.5 f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 1.1 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.6 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.55 1. data based on characterization results, not tested in production. 2. default clock configuration m easured with all peripherals off.
electrical characteristics stm8s207xx, stm8s208xx 58/103 doc id 14733 rev 12 table 21. total current consumption with code execution in run mode at v dd = 3.3 v symbol parameter conditions typ max (1) unit i dd(run) supply current in run mode, code executed from ram f cpu = f master = 24 mhz, t a 105 c hse crystal osc. (24 mhz) 4.0 ma hse user ext. clock (24 mhz) 3.7 7.3 f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 2.9 hse user ext. clock (16 mhz) 2.7 5.8 hsi rc osc. (16 mhz) 2.5 3.4 f cpu = f master /128 = 125 khz hse user ext. clock (16 mhz) 1.2 4.1 hsi rc osc. (16 mhz) 1.0 1.3 f cpu = f master /128 = 15.625 khz hsi rc osc. (16mhz/8) 0.55 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.45 supply current in run mode, code executed from flash f cpu = f master = 24 mhz, t a 105 c hse crystal osc. (24 mhz) 11.0 hse user ext. clock (24 mhz) 10.8 18.0 f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 8.4 hse user ext. clock (16 mhz) 8.2 15.2 hsi rc osc. (16 mhz) 8.1 13.2 f cpu = f master = 2 mhz. hsi rc osc. (16 mhz/8) (2) 1.5 f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 1.1 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.6 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.55 1. data based on characterization results, not tested in production. 2. default clock configuration.
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 59/103 total current consumption in wait mode table 22. total current consumption in wait mode at v dd = 5 v symbol parameter conditions typ max (1) unit i dd(wfi) supply current in wait mode f cpu = f master = 24 mhz, t a 105 c hse crystal osc. (24 mhz) 2.4 ma hse user ext. clock (24 mhz) 1.8 4.7 f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 2.0 hse user ext. clock (16 mhz) 1.4 4.4 hsi rc osc. (16 mhz) 1.2 1.6 f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 1.0 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) (2) 0.55 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.5 1. data based on characterization results, not tested in production. 2. default clock configuration m easured with all peripherals off. table 23. total current consumption in wait mode at v dd = 3.3 v symbol parameter conditions typ max (1) unit i dd(wfi) supply current in wait mode f cpu = f master = 24 mhz, t a 105 c hse crystal osc. (24 mhz) 2.0 ma hse user ext. clock (24 mhz) 1.8 4.7 f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 1.6 hse user ext. clock (16 mhz) 1.4 4.4 hsi rc osc. (16 mhz) 1.2 1.6 f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 1.0 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) (2) 0.55 f cpu = f master /128 = 15.625 khz lsi rc osc. (128 khz) 0.5 1. data based on characterization results, not tested in production. 2. default clock configuration m easured with all peripherals off.
electrical characteristics stm8s207xx, stm8s208xx 60/103 doc id 14733 rev 12 total current consumption in active halt mode table 24. total current consumption in active halt mode at v dd = 5 v, t a -40 to 85 c symbol parameter conditions typ max (1) unit main voltage regulator (mvr) (2) flash mode (3) clock source i dd(ah) supply current in active halt mode on operating mode hse crystal oscillator (16 mhz) 1000 a lsi rc oscillator (128 khz) 200 260 powerdown mode hse crystal oscillator (16 mhz) 940 lsi rc oscillator (128 khz) 140 off operating mode lsi rc oscillator 128 khz) 68 powerdown mode 11 45 1. data based on characterization results, not tested in production. 2. configured by the regah bit in the clk_ickr register. 3. configured by the ahalt bit in the flash_cr1 register. table 25. total current consumption in active halt mode at v dd = 3.3 v symbol parameter conditions typ (1) unit main voltage regulator (mvr) (2) flash mode (3) clock source i dd(ah) supply current in active halt mode on operating mode hse crystal osc. (16 mhz) 600 a lsi rc osc. (128 khz) 200 powerdown mode hse crystal osc. (16 mhz) 540 lsi rc osc. (128 khz) 140 off operating mode lsi rc osc. (128 khz) 66 powerdown mode 9 1. data based on characterization results, not tested in production. 2. configured by the regah bit in the clk_ickr register. 3. configured by the ahalt bit in the flash_cr1 register.
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 61/103 total current consumption in halt mode low power mode wakeup times table 26. total current consumption in halt mode at v dd = 5 v symbol parameter conditions typ max at 85 c max at 125 c unit i dd(h) supply current in halt mode flash in operating mode, hsi clock after wakeup 63.5 a flash in powerdown mode, hsi clock after wakeup 6.5 35 100 table 27. total current consumption in halt mode at v dd = 3.3 v symbol parameter conditions typ unit i dd(h) supply current in halt mode flash in operating mode, hsi clock after wakeup 61.5 a flash in powerdown mode, hsi clock after wakeup 4.5 table 28. wakeup times symbol parameter conditions typ max (1) unit t wu(wfi) wakeup time from wait mode to run mode (3) see note (2) s f cpu = f master = 16 mhz. 0.56 t wu(ah) wakeup time active halt mode to run mode. (3) mvr voltage regulator on (4) flash in operating mode (5) hsi (after wakeup) 1 (6) 2 (6) flash in powerdown mode (5) 3 (6) mvr voltage regulator off (4) flash in operating mode (5) 48 (6) flash in powerdown mode (5) 50 (6) t wu(h) wakeup time from halt mode to run mode (3) flash in operating mode (5) 52 flash in powerdown mode (5) 54 1. data guaranteed by design, not tested in production. 2. t wu(wfi) = 2 x 1/f master + 7 x 1/f cpu 3. measured from interrupt event to interrupt vector fetch. 4. configured by the regah bit in the clk_ickr register. 5. configured by the ahalt bit in the flash_cr1 register. 6. plus 1 lsi clock depending on synchronization.
electrical characteristics stm8s207xx, stm8s208xx 62/103 doc id 14733 rev 12 total current consumption and timing in forced reset state current consumption of on-chip peripherals subject to general operating conditions for v dd and t a . hsi internal rc/f cpu = f master = 16 mhz. table 29. total current consumption and timing in forced reset state symbol parameter conditions typ max (1) unit i dd(r) supply current in reset state v dd = 5 v 1.6 ma v dd = 3.3 v 0.8 t resetbl reset release to bootloader vector fetch 150 s 1. data guaranteed by design, not tested in production. table 30. peripheral current consumption symbol parameter typ. unit i dd(tim1) tim1 supply current (1) 1. data based on a differential i dd measurement between reset configur ation and timer counter running at 16 mhz. no ic/oc programmed (no i/o pads toggling). not tested in production. 220 a i dd(tim2) tim2 supply current (1) 120 i dd(tim3) tim3 timer supply current (1) 100 i dd(tim4) tim4 timer supply current (1) 25 i dd(uart1) uart1 supply current (2) 2. data based on a differential i dd measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. no i/o pads toggling. not tested in production. 90 i dd(uart3) uart3 supply current (2) 110 i dd(spi) spi supply current (2) 40 i dd(i 2 c) i 2 c supply current (2) 50 i dd(can) becan supply current (2) 210 i dd(adc2) adc2 supply current when converting (3) 3. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. not tested in production. 1000
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 63/103 current consumption curves figure 14 and figure 15 show typical current consumption measured with code executing in ram. figure 14. typ. i dd(run) vs v dd , hsi rc osc, f cpu = 16 mhz figure 15. typ. i dd(wfi) vs v dd , hsi rc osc, f cpu = 16 mhz 0 0.5 1 1.5 2 2.5 3 3.5 4 2.5 3 3.5 4 4.5 5 5.5 6 -40?c 25?c 85?c 125?c i dd(run)hsi [ma] v dd [v] 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 6 -40?c 25?c 85?c 125?c v dd [v] i dd(wfi)hsi [ma]
electrical characteristics stm8s207xx, stm8s208xx 64/103 doc id 14733 rev 12 10.3.3 external clock sources and timing characteristics hse user external clock subject to general operating conditions for v dd and t a . figure 16. hse external clock source hse crystal/ceramic resonator oscillator the hse clock can be supplied with a 1 to 24 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscilla tor pins in order to minimize output distortion and start-up stabilizatio n time. refer to the crystal resona tor manufacturer for more details (frequency, package, accuracy...). table 31. hse user external clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency 024mhz v hseh (1) 1. data based on characterization results, not tested in production. oscin input pin high level voltage 0.7 x v dd v dd + 0.3 v v v hsel (1) oscin input pin low level voltage v ss 0.3 x v dd i leak_hse oscin input leakage current v ss < v in < v dd -1 1 a oscin f hse external clock stm8 source v hsel v hseh
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 65/103 figure 17. hse oscillator circuit diagram hse oscillator critical g m formula r m : notional resistance (see crystal specification) l m : notional inductance (see crystal specification) c m : notional capacitance (s ee crystal specification) co: shunt capacitance (see crystal specification) c l1 =c l2 =c: grounded external capacitance g m >> g mcrit table 32. hse oscillator characteristics symbol parameter conditions min typ max unit f hse external high speed oscillator frequency 124mhz r f feedback resistor 220 k c (1) recommended load capacitance (2) 20 pf i dd(hse) hse oscillator power consumption c = 20 pf, f osc = 24 mhz 6 (startup) 2 (stabilized) (3) ma c = 10 pf, f osc = 24 mhz 6 (startup) 1.5 (stabilized) (3) g m oscillator transconductance 5 ma/v t su(hse) (4) startup time v dd is stabilized 1 ms 1. c is approximately equivalent to 2 x crystal cload. 2. the oscillator selection can be optimized in terms of supply current using a high qual ity resonator with small r m value. refer to crystal manufacturer for more details 3. data based on characterization results, not tested in production. 4. t su(hse) is the start-up time measured from the moment it is enabled (by software) to a stabi lized 24 mhz oscillation is reached. this value is measured for a standar d crystal resonator and it can vary signi ficantly with the crystal manufacturer. oscout oscin f hse to core c l1 c l2 r f stm8 resonator consumption control g m r m c m l m c o resonator g mcrit 2 f hse () 2 r m 2co c + () 2 =
electrical characteristics stm8s207xx, stm8s208xx 66/103 doc id 14733 rev 12 10.3.4 internal clock sources and timing characteristics subject to general operating conditions for v dd and t a . f hse high speed internal rc oscillator (hsi) figure 18. typical hsi frequency variation vs v dd at 4 temperatures table 33. hsi oscillator characteristics symbol parameter conditions min typ max unit f hsi frequency 16 mhz acc hsi accuracy of hsi oscillator tr i m m e d b y t h e clk_hsitrimr register for given v dd and t a conditions -1.0 (1) 1. guaranteeed by design, not tested in production. 1 .0 % accuracy of hsi oscillator (factory calibrated) v dd = 5 v, t a = 25 c -1.5 1.5 v dd = 5 v, 25 c t a 85 c -2.2 2.2 2.95 v v dd 5.5 v, -40 c t a 125 c -3.0 (2) 2. data based on characterization results, not tested in production 3.0 (2) t su(hsi) hsi oscillator wakeup time including calibration 1.0 (1) s i dd(hsi) hsi oscillator power consumption 170 250 (2) a -3% -2% -1% 0% 1% 2% 3% 2.5 3 3.5 4 4.5 5 5.5 6 -40?c 25?c 85?c 125?c ai15067 v dd (v) % accuracy
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 67/103 low speed internal rc oscillator (lsi) subject to general operating conditions for v dd and t a . figure 19. typical lsi frequency variation vs v dd @ 25 c table 34. lsi oscillator characteristics symbol parameter conditions min typ max unit f lsi frequency 110 128 146 khz t su(lsi) lsi oscillator wakeup time 7 (1) 1. guaranteeed by design, not tested in production. s i dd(lsi) lsi oscillator power consumption 5 a ai15070 -3% -2% -1% 0% 1% 2% 3% 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] % accuracy
electrical characteristics stm8s207xx, stm8s208xx 68/103 doc id 14733 rev 12 10.3.5 memory characteristics ram and hardware registers flash program memory/data eeprom memory general conditions: t a = -40 to 125 c . table 35. ram and hardware registers symbol parameter conditions min unit v rm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guarant eed by design, not tested in production. halt mode (or reset) v it-max (2) 2. refer to table 19 on page 56 for the value of v it-max . v table 36. flash program memory/data eeprom memory symbol parameter conditions min (1) 1. data based on characterization results, not tested in production. typ max unit v dd operating voltage (all modes, execution/write/erase) f cpu 24 mhz 2.95 5.5 v t prog standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) 66.6ms fast programming time for 1 block (128 bytes) 33.3ms t erase erase time for 1 block (128 bytes) 3 3.3 ms n rw erase/write cycles (2) (program memory) 2. the physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. t a = 85 c 10 k cycles erase/write cycles (data memory) (2) t a = 125 c 300 k 1m t ret data retention (program memory) after 10 k erase/write cycles at t a = 85 c t ret = 55 c 20 years data retention (data memory) after 10 k erase/write cycles at t a = 85 c t ret = 55 c 20 data retention (data memory) after 300k erase/write cycles at t a = 125 c t ret = 85 c 1 i dd supply current (flash programming or erasing for 1 to 128 bytes) 2ma
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 69/103 10.3.6 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor. table 37. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage v dd = 5 v -0.3 0.3 x v dd v v ih input high level voltage 0.7 x v dd v dd + 0.3 v v hys hysteresis (1) 700 mv r pu pull-up resistor v dd = 5 v, v in = v ss 30 55 80 k t r , t f rise and fall time (10% - 90%) fast i/os load = 50 pf 20 (2) ns standard and high sink i/os load = 50 pf 125 (2) fast i/os load = 20 pf 35 (3) standard and high sink i/os load = 20 pf 125 (3) i lkg input leakage current, analog and digital v ss v in v dd 1 a i lkg ana analog input leakage current v ss v in v dd 250 (2) na i lkg(inj) leakage current in adjacent i/o (2) injection current 4 ma 1 (2) a 1. hysteresis voltage between schmitt trigger switching levels . based on characterization results, not tested in production. 2. data based on characterization results, not tested in production. 3. guaranteed by design.
electrical characteristics stm8s207xx, stm8s208xx 70/103 doc id 14733 rev 12 figure 20. typical v il and v ih vs v dd @ 4 temperatures figure 21. typical pull-up resistance vs v dd @ 4 temperatures figure 22. typical pull-up current vs v dd @ 4 temperatures 1. the pull-up is a pure resi stor (slope goes through 0). 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 6 -40?c 25?c 85?c 125?c v il /v ih [v] v dd [v] 30 35 40 45 50 55 60 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] -40?c 25?c 85?c 125?c pull-up resistance [ w] 0 20 40 60 80 100 120 140 0123456 v dd [v] pull-up current [a] -40?c 25?c 85?c 125?c ai15068
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 71/103 table 38. output driving current (standard ports) symbol parameter conditions min max unit v ol output low level with 8 pins sunk i io = 10 ma, v dd = 5 v 2 v output low level with 4 pins sunk i io = 4 ma, v dd = 3.3 v 1 (1) v oh output high level with 8 pins sourced i io = 10 ma, v dd = 5 v 2.8 v output high level with 4 pins sourced i io = 4 ma, v dd = 3.3 v 2.1 (1) 1. data based on characterization results, not tested in production table 39. output driving current (true open drain ports) symbol parameter conditions max unit v ol output low level with 2 pins sunk i io = 10 ma, v dd = 5 v 1 v i io = 10 ma, v dd = 3.3 v 1.5 (1) i io = 20 ma, v dd = 5 v 2 (1) 1. data based on characterization results, not tested in production table 40. output driving current (high sink ports) symbol parameter conditions min max unit v ol output low level with 8 pins sunk i io = 10 ma,v dd = 5 v 0.8 v output low level with 4 pins sunk i io = 10 ma,v dd = 3.3 v 1 (1) output low level with 4 pins sunk i io = 20 ma,v dd = 5 v 1.5 (1) v oh output high level with 8 pins sourced i io = 10 ma, v dd = 5 v 4.0 output high level with 4 pins sourced i io = 10 ma, v dd = 3.3 v 2.1 (1) output high level with 4 pins sourced i io = 20 ma, v dd = 5 v 3.3 (1) 1. data based on characterization results, not tested in production
electrical characteristics stm8s207xx, stm8s208xx 72/103 doc id 14733 rev 12 typical output level curves figure 24 to figure 31 show typical output level curves measured with output on a single pin. figure 23. typ. v ol @ v dd = 5 v (standard ports) figure 24. typ. v ol @ v dd = 3.3 v (standard ports) figure 25. typ. v ol @ v dd = 5 v (true open drain ports) 0 0.25 0.5 0.75 1 1.25 1.5 024681012 -40?c 25?c 85?c 125?c i ol [ma] v ol [v] 0 0.25 0.5 0.75 1 1.25 1.5 01234567 -40?c 25?c 85?c 125?c vol [v] v ol [v] i ol [ma] 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 5 10 15 20 25 -40?c 25?c 85?c 125?c v ol [v] i ol [ma]
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 73/103 figure 26. typ. v ol @ v dd = 3.3 v (true open drain ports) figure 27. typ. v ol @ v dd = 5 v (high sink ports) figure 28. typ. v ol @ v dd = 3.3 v (high sink ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 02468101214 -40?c 25?c 85?c 125?c i ol [ma] v ol [v] 0 0.25 0.5 0.75 1 1.25 1.5 0 5 10 15 20 25 -40?c 25?c 85?c 125?c i ol [ma] v ol [v] 0 0.25 0.5 0.75 1 1.25 1.5 02468101214 -40?c 25?c 85?c 125?c i ol [ma] v ol [v]
electrical characteristics stm8s207xx, stm8s208xx 74/103 doc id 14733 rev 12 figure 29. typ. v dd - v oh @ v dd = 5 v (standard ports) figure 30. typ. v dd - v oh @ v dd = 3.3 v (standard ports) figure 31. typ. v dd - v oh @ v dd = 5 v (high sink ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 024681012 -40?c 25?c 85?c 125?c v dd - v oh [v] i ol [ma] 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 01234567 -40?c 25?c 85?c 125?c i ol [ma] v dd - v oh [v] 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 5 10 15 20 25 -40?c 25?c 85?c 125?c i ol [ma] v dd - v oh [v]
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 75/103 figure 32. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) 10.3.7 reset pin characteristics subject to general operating conditions for v dd and t a unless otherwise specified. figure 33. typical nrst v il and v ih vs v dd @ 4 temperatures 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 02468101214 -40?c 25?c 85?c 125?c i ol [ma] v dd - v oh [v] table 41. nrst pin characteristics symbol parameter conditions min typ 1) max unit v il(nrst) nrst input low level voltage (1) -0.3 v 0.3 x v dd v v ih(nrst) nrst input high level voltage (1) 0.7 x v dd v dd + 0.3 v ol(nrst) nrst output low level voltage (1) i ol = 2 ma 0.5 r pu(nrst) nrst pull-up resistor (2) 30 55 80 k t ifp(nrst) nrst input filtered pulse (3) 75 ns t infp(nrst) nrst input not filtered pulse (3) 500 ns t op(nrst) nrst output pulse (1) 15 s 1. data based on characterization results, not tested in production. 2. the r pu pull-up equivalent resistor is based on a resistive transistor 3. data guaranteed by design, not tested in production. 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 6 -40?c 25?c 85?c 125?c v dd [v] v il /v ih [v]
electrical characteristics stm8s207xx, stm8s208xx 76/103 doc id 14733 rev 12 figure 34. typical nrst pull-up resistance vs v dd @ 4 temperatures figure 35. typical nrst pull-up current vs v dd @ 4 temperatures the reset network shown in figure 36 protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below the v il max. level specified in ta bl e 41 . otherwise the reset is not taken into account internally. for power consumption sensitive applications, the capacity of the external reset capacitor can be reduced to limit charge/discharge current. if the nrstsignal is used to reset the external circuitry, care must be taken of the charge/discharge time of the ex ternal capacitor to fulfill the external device?s reset timing conditions. the minimum recommended capacity is 10 nf. figure 36. recommended reset pin protection 30 35 40 45 50 55 60 2.5 3 3.5 4 4.5 5 5.5 6 -40?c 25?c 85?c 125?c v dd [v] nreset pull-up resistance [ w] 0 20 40 60 80 100 120 140 0123456 v dd [v] nreset pull-up current [a] -40?c 25?c 85?c 125?c ai15069 0.1f external reset circuit stm8 filter r pu v dd internal reset nrst (optional)
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 77/103 10.3.8 spi serial peripheral interface unless otherwise specified, the parameters given in ta bl e 42 are derived from tests performed under ambient temperature, f master frequency and v dd supply voltage conditions. t master = 1/f master . refer to i/o port characteristics for more details on the input/output alternate function characteristics (nss , sck, mosi, miso). table 42. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 0 10 mhz slave mode 0 6 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf 25 ns t su(nss) (1) nss setup time slave mode 4 x t master t h(nss) (1) nss hold time slave mode 70 t w(sckh) (1) t w(sckl) (1) sck high and low time master mode t sck /2 - 15 t sck /2 + 15 t su(mi) (1) t su(si) (1) data input setup time master mode 5 slave mode 5 t h(mi) (1) t h(si) (1) data input hold time master mode 7 slave mode 10 t a(so) (1)(2) data output access time slave mode 3 x t master t dis(so) (1)(3) data output disable time slave mode 25 t v(so) (1) data output valid time slave mode (after enable edge) 75 t v(mo) (1) data output valid time master mode (after enable edge) 30 t h(so) (1) data output hold time slave mode (after enable edge) 31 t h(mo) (1) master mode (after enable edge) 12 1. values based on design simulation and/or charac terization results, and not tested in production. 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z.
electrical characteristics stm8s207xx, stm8s208xx 78/103 doc id 14733 rev 12 figure 37. spi timing diagram - slave mode and cpha = 0 figure 38. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd. ai14134 sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 79/103 figure 39. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd. ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo)
electrical characteristics stm8s207xx, stm8s208xx 80/103 doc id 14733 rev 12 10.3.9 i 2 c interface characteristics table 43. i 2 c characteristics symbol parameter standard mode i 2 c fast mode i 2 c (1) 1. f master , must be at least 8 mhz to achieve max fast i 2 c speed (400khz) unit min (2) 2. data based on standard i 2 c protocol requirement, not tested in production max (2) min (2) max (2) t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low time 0 (4) 4. the device must internally provide a hold time of at least 300 ns for th e sda signal in order to bridge the undefined region of the falling edge of scl 900 (3) t r(sda) t r(scl) sda and scl rise time 1000 300 t f(sda) t f(scl) sda and scl fall time 300 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 81/103 figure 40. typical application with i 2 c bus and timing diagram 1. measurement points are made at cmos levels: 0.3 x v dd and 0.7 x v dd ai 34!24 3$ ! )#bus 6 $$ 6 $$ 34-3xxx 3$! 3#, t f3$! t r3$! 3#, t h34! t w3#,( t w3#,, t su3$! t r3#, t f3#, t h3$! 3 4!242%0%!4%$ 34!24 t su34! t su34/ 34/0 t su34!34/
electrical characteristics stm8s207xx, stm8s208xx 82/103 doc id 14733 rev 12 10.3.10 10-bit adc characteristics subject to general operating conditions for v dda , f master , and t a unless otherwise specified. table 44. adc characteristics symbol parameter conditions min typ max unit f adc adc clock frequency v dda = 3 to 5.5 v 1 4 mhz v dda = 4.5 to 5.5 v 1 6 v dda analog supply 3 5.5 v v ref+ positive reference voltage 2.75 (1) 1. data guaranteed by design, not tested in production.. v dda v v ref- negative reference voltage v ssa 0.5 (1) v v ain conversion voltage range (2) 2. during the sample time the input capacitance c ain (3 pf max) can be char ged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s. after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t s depend on programming. v ssa v dda v devices with external v ref+ /v ref- pins v ref- v ref+ v c adc internal sample and hold capacitor 3pf t s (2) sampling time f adc = 4 mhz 0.75 s f adc = 6 mhz 0.5 t stab wakeup time from standby 7 s t conv total conversion time (including sampling time, 10-bit resolution) f adc = 4 mhz 3.5 s f adc = 6 mhz 2.33 s 14 1/f adc
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 83/103 table 45. adc accuracy with r ain < 10 k , v dda = 5 v symbol parameter conditions typ max (1) 1. data based on characterisation results for lqfp80 device with v ref+ /v ref- , not tested in production. unit |e t | total unadjusted error (2) 2. adc accuracy vs. negative injection current: injecti ng negative current on any of the analog input pins should be avoided as this significant ly reduces the accuracy of the conversion being per formed on another analog input. it is recommended to add a schottky diode (p in to ground) to standard analog pins which may potentially inject negative current. any positive inje ction current within the limits specified for i inj(pin) and i inj(pin) in section 10.3.6 does not affect the adc accuracy. f adc = 2 mhz 1 2.5 lsb f adc = 4 mhz 1.4 3 f adc = 6 mhz 1.6 3.5 |e o | offset error (2) f adc = 2 mhz 0.6 2 f adc = 4 mhz 1.1 2.5 f adc = 6 mhz 1.2 2.5 |e g | gain error (2) f adc = 2 mhz 0.2 2 f adc = 4 mhz 0.6 2.5 f adc = 6 mhz 0.8 2.5 |e d | differential linearity error (2) f adc = 2 mhz 0.7 1.5 f adc = 4 mhz 0.7 1.5 f adc = 6 mhz 0.8 1.5 |e l | integral linearity error (2) f adc = 2 mhz 0.6 1.5 f adc = 4 mhz 0.6 1.5 f adc = 6 mhz 0.6 1.5 table 46. adc accuracy with r ain < 10 k r ain , v dda = 3.3 v symbol parameter conditions typ max (1) unit |e t | total unadjusted error (2) f adc = 2 mhz 1.1 2 lsb f adc = 4 mhz 1.6 2.5 |e o | offset error (2) f adc = 2 mhz 0.7 1.5 f adc = 4 mhz 1.3 2 |e g | gain error (2) f adc = 2 mhz 0.2 1.5 f adc = 4 mhz 0.5 2 |e d | differential linearity error (2) f adc = 2 mhz 0.7 1 f adc = 4 mhz 0.7 1 |e l | integral linearity error (2) f adc = 2 mhz 0.6 1.5 f adc = 4 mhz 0.6 1.5
electrical characteristics stm8s207xx, stm8s208xx 84/103 doc id 14733 rev 12 figure 41. adc accura cy characteristics 1. example of an actual transfer curve. 2. the ideal transfer curve 3. end point correlation line e t = total unadjusted error: maximum deviation betw een the actual and the ideal transfer curves. e o = offset error: deviation between the firs t actual transition and the first ideal one. e g = gain error: deviation between the last ideal transition and the last actual one. e d = differential linearity error: maximum dev iation between actual steps and the ideal one. e l = integral linearity error: maximum deviation between any actual transition an d the end point correlation line. figure 42. typical application with adc e o e g 1lsb ideal 1lsb ideal v dda v ssa ? 1024 ---------------------------------------- - = 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021102210231024 (1) (2) e t e d e l (3) v dda v ssa ainx stm8 v dd i l 1a v t 0.6v v t 0.6v c adc v ain r ain 10-bit a/d conversion c ain
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 85/103 10.3.11 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. functional ems (electromagnetic susceptibility) while executing a simple application (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the leds). esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 61000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a function al disturbance occurs. this test conforms with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the nr st pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 47. ems data symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5 v, t a = 25 c, f master = 16 mhz, conforming to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100pf on v dd and v ss pins to induce a functional disturbance v dd = 5 v, t a = 25 c, f master = 16 mhz, conforming to iec 61000-4-4 4a
electrical characteristics stm8s207xx, stm8s208xx 86/103 doc id 14733 rev 12 electromagnetic interference (emi) emission tests conform to the sae iec 61967-2 st andard for test software, board layout and pin loading. absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (3 positive then 3 n egative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22-a114a/a115a standard. for more details, refer to the application note an1181. table 48. emi data symbol parameter conditions unit general conditions monitored frequency band max f hse /f cpu (1) 8 mhz/ 8 mhz 8 mhz/ 16 mhz 8 mhz/ 24 mhz s emi peak level v dd = 5 v t a = 25 c lqfp80 package conforming to sae iec 61967-2 0.1mhz to 30 mhz 15 20 24 dbv 30 mhz to 130 mhz 18 21 16 130 mhz to 1 ghz -1 1 4 sae emi level sae emi level 2 2.5 2.5 1. data based on characterization results, not tested in production. table 49. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = 25c, conforming to jesd22-a114 a2000v v esd(cdm) electrostatic discharge voltage (charge device model) t a = 25c, conforming to jesd22-c101 iv 1000 v
stm8s207xx, stm8s208xx electrical characteristics doc id 14733 rev 12 87/103 static latch-up two complementary static tests are required on 10 parts to assess the latch-up performance: a supply overvoltage (applied to each power supply pin) a current injection (applied to each input, output and configurable i/o pin) is performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. table 50. electrical sensitivities symbol parameter conditions class (1) 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). lu static latch-up class t a = 25 c a t a = 85 c a t a = 125 c a
package characteristics stm8s207xx, stm8s208xx 88/103 doc id 14733 rev 12 11 package characteristics to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at www.st.com . ecopack? is an st trademark.
stm8s207xx, stm8s208xx package characteristics doc id 14733 rev 12 89/103 11.1 package mechanical data 11.1.1 lqfp package mechanical data figure 43. 80-pin low profile quad flat package (14 x 14) table 51. 80-pin low profile quad flat package mechanical data symbol mm inches (1) 1. values in inches are converted fr om mm and rounded to four decimal places. min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.220 0.320 0.380 0.0087 0.0126 0.0150 c 0.090 0.200 0.0035 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 12.350 0.4862 e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 12.350 0.4862 e 0.650 0.0256 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.100 0.0039 1s_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 40 41 60 61 b 80 1 pin 1 identification
package characteristics stm8s207xx, stm8s208xx 90/103 doc id 14733 rev 12 figure 44. 64-pin low profile quad flat package (14 x 14) table 52. 64-pin low profile quad flat package mechanical data (14 x 14) symbol mm inches (1) 1. values in inches are converted fr om mm and rounded to four decimal places. min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 0.200 0.0035 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 12.000 0.4724 e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 12.000 0.4724 e 0.800 0.0315 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.100 0.0039 1r_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 32 33 48 49 b 64 1 pin 1 identification 16 17
stm8s207xx, stm8s208xx package characteristics doc id 14733 rev 12 91/103 figure 45. 64-pin low profile quad flat package (10 x 10) table 53. 64-pin low profile quad flat package mechanical data (10 x 10) symbol mm inches (1) 1. values in inches are converted fr om mm and rounded to four decimal places. min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 12.000 0.4724 d1 10.000 0.3937 e 12.000 0.4724 e1 10.000 0.3937 e 0.500 0.0197 k 0.000 3.500 7.000 0.0000 3.5000 7.0000 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 5w_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 32 33 48 49 b 64 1 pin 1 identification 16 17
package characteristics stm8s207xx, stm8s208xx 92/103 doc id 14733 rev 12 figure 46. 48-pin low profile quad flat package (7 x 7) table 54. 48-pin low profile quad flat package mechanical data symbol mm inches (1) 1. values in inches are converted fr om mm and rounded to four decimal places. min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 5.500 0.2165 e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 5.500 0.2165 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.080 0.0031 5b_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 24 25 36 37 b 48 1 pin 1 identification 12 13
stm8s207xx, stm8s208xx package characteristics doc id 14733 rev 12 93/103 figure 47. 44-pin low profile quad flat package (10 x 10) table 55. 44-pin low profile quad flat package mechanical data symbol mm inches (1) 1. values in inches are converted fr om mm and rounded to four decimal places. min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 0.200 0.0035 0.0079 d 11.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3858 0.3937 0.4016 d3 8.000 0.3150 e 11.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.000 10.200 0.3858 0.3937 0.4016 e3 8.000 0.3150 e 0.800 0.0315 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.100 0.0039 4y_me l a1 k l1 c a a2 d d1 d3 e3 e1 e 22 23 33 34 b 44 1 pin 1 identification 11 12 ccc c
package characteristics stm8s207xx, stm8s208xx 94/103 doc id 14733 rev 12 figure 48. 32-pin low profile quad flat package (7 x 7) table 56. 32-pin low profile quad flat package mechanical data symbol mm inches (1) 1. values in inches are converted fr om mm and rounded to four decimal places. min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 5.600 0.2205 e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 5.600 0.2205 e 0.800 0.0315 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.100 0.0039 l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 16 17 24 25 b 32 1 pin 1 identification 8 9
stm8s207xx, stm8s208xx package characteristics doc id 14733 rev 12 95/103 11.2 thermal characteristics the maximum chip junction temperature (t jmax ) must never exceed the values given in ta bl e 18: general operating conditions on page 55 . the maximum chip-junction temperature, t jmax , in degrees celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: t amax is the maximum ambient temperature in c ja is the package junction-to-ambient thermal resistance in c/w p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) p intmax is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/omax represents the maximum power dissipation on output pins, where: p i/omax = (v ol *i ol ) + ((v dd -v oh) *i oh ), and taking account of the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the application. 11.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 57. thermal characteristics (1) 1. thermal resistances are based on jedec jesd51- 2 with 4-layer pcb in a natural convection environment. symbol parameter value unit ja thermal resistance junction-ambient lqfp 80 - 14 x 14 mm 38 c/w ja thermal resistance junction-ambient lqfp 64 - 14 x 14 mm 45 c/w ja thermal resistance junction-ambient lqfp 64 - 10 x 10 mm 46 c/w ja thermal resistance junction-ambient lqfp 48 - 7 x 7 mm 57 c/w ja thermal resistance junction-ambient lqfp 44 - 10 x 10 mm 54 c/w ja thermal resistance junction-ambient lqfp 32 - 7 x 7 mm 60 c/w
package characteristics stm8s207xx, stm8s208xx 96/103 doc id 14733 rev 12 11.2.2 selecting the pro duct temperature range when ordering the microcontroller, the temperature range is specified in the order code (see figure 49: stm8s207xx/208xx performance line ordering information scheme(1) on page 99 ). the following example shows how to calculate the temperature range needed for a given application. assuming the following application conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2) i ddmax = 15 ma, v dd = 5.5 v maximum eight standard i/os used at the same time in output at low level with i ol = 10 ma, v ol = 2 v maximum four high sink i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.5 v maximum two true open drain i/os used at the same time in output at low level with i ol = 20 ma, v ol = 2 v p intmax = 15 ma x 5.5 v = 82.5 mw p iomax = (10 ma x 2 v x 8 ) + (20 ma x 2 v x 2) + (20 ma x 1.5 v x 4) = 360 mw this gives: p intmax = 82.5 mw and p iomax 360 mw: p dmax = 82.5 mw + 360 mw thus: p dmax = 443 mw using the values obtained in ta b l e 57: thermal characteristics on page 95 t jmax is calculated as follows for lqfp64 10 x 10 mm = 46 c/w: t jmax = 82 c + (46 c/w x 443 mw) = 82 c + 20 c = 102 c this is within the range of the suffix 6 version parts (-40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suffix 6.
stm8s207xx, stm8s208xx stm8 development tools doc id 14733 rev 12 97/103 12 stm8 development tools development tools for the stm8 microcontrollers include the full-featured stice emulation system supported by a complete software tool package including c compiler, assembler and integrated development environment with high-level language debugger. in addition, the stm8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 12.1 emulation and in-circuit debugging tools the stice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effec tiveness. in addition, stm8 application development is supported by a low-cost in-circuit debugger/programmer. the stice is the fourth generation of full featured emulators from stmicroelectronics. it offers new advanced debugging capabilities incl uding profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. in addition, stice offers in-circuit debugging and programming of stm8 microcontrollers via the stm8 single wire interface module (swim), which allows non- intrusive debugging of an application while it runs on the target microcontroller. for improved cost effectiveness, stice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future st microcontrollers. stice key features occurrence and time profiling and code coverage (new features) advanced breakpoints with up to 4 levels of conditions data breakpoints program and data trace recording up to 128 kb records read/write on the fly of memory during emulation in-circuit debugging/programming via swim protocol 8-bit probe analyzer 1 input and 2 output triggers power supply follower managing application voltages between 1.62 to 5.5 v modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements supported by free software tools that include integrated development environment (ide), programming software interface and assembler for stm8.
stm8 development tools stm8s207xx, stm8s208xx 98/103 doc id 14733 rev 12 12.2 software tools stm8 development tools are supported by a complete, free software package from stmicroelectronics that includes st vis ual develop (stvd) ide and the st visual programmer (stvp) software interface. stvd provides seamless integration of the cosmic and raisonance c compilers for stm8. a free version that outputs up to 32 kbytes of code is available. 12.2.1 stm8 toolset stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www.st.com/mcu. this package includes: st visual develop ? full-featured integrated development environment from st, featuring seamless integration of c and asm toolsets full-featured debugger project management syntax highlighting editor integrated programming interface support of advanced emulation features fo r stice such as code profiling and coverage st visual programmer (stvp) ? easy-to-use, unlimited graphical interface allowing read, write and verify of your st m8 microcontroller?s flash pr ogram memory, data eeprom and option bytes. stvp also offers project mode for saving programming configurations and automating programming sequences. 12.2.2 c and assembly toolchains control of c and assembly toolchains is seam lessly integrated into the stvd integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. available toolchains include: cosmic c compiler for stm8 ? one free version that outputs up to 32 kbytes of code is available. for more informat ion, see www.cosmic-software.com. raisonance c compiler for stm8 ? one free version that outputs up to 32 kbytes of code. for more information, see www.raisonance.com. stm8 assembler linker ? free assembly toolchain included in the stvd toolset, which allows you to assemble and link your application source code. 12.3 programming tools during the development cycle, stice provides in-circuit programming of the stm8 flash microcontroller on your application board via the swim protocol. additional tools are to include a low-cost in-circuit programmer as well as st socket boards, which provide dedicated programming platforms with sockets for programming your stm8. for production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the stm8 family.
stm8s207xx, stm8s208xx ordering information doc id 14733 rev 12 99/103 13 ordering information figure 49. stm8s207xx/208xx performance line ordering information scheme (1) 1. for a list of available options (e.g. memory size, package) and or derable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the st sales office nearest to you. 2. refer to table 2: stm8s20xxx performance line features for detailed description. stm8 s 208 m b t 6 b tr product class stm8 microcontroller pin count k = 32 pins s = 44 pins c = 48 pins r = 64 pins m = 80 pins package type t = lqfp example: sub-family type (2) 208 = full peripheral set 207 = intermediate peripheral set family type s = standard temperature range 3 = -40 c to 125 c 6 = -40 c to 85 c program memory size 6 = 32 kbyte 8 = 64 kbyte b = 128 kbyte package pitch no character = 0.5 mm b = 0.65 mm c = 0.8 mm packing no character = tray or tube tr = tape and reel
revision history stm8s207xx, stm8s208xx 100/103 doc id 14733 rev 12 14 revision history table 58. document revision history date revision changes 23-may-2008 1 initial release. 05-jun-2008 2 added part numbers on page 1 and in table 2 on page 11 . updated section 4: product overview . updated section 10: electrical characteristics . 22-jun-2008 3 added part numbers on page 1 and in table 2 on page 11 . 12-aug-2008 4 added 32 pin device pinout and ordering information. updated ubc option description in table 13 on page 47 . usart renamed uart1, linuart renamed uart3. max. adc frequency increased to 6 mhz. 20-oct-2008 5 removed stm8s207k4 part number. removed lqfp64 14 x 14 mm package. added medium and high density flash memory categories. added section 6: memory and register map on page 33 . replaced becan3 by becan in section 4.14.5: becan . updated section 10: electrical characteristics on page 51 . updated lqfp44 ( figure 47 and table 55 ), and lqfp32 outline and mechanical data ( figure 48 , and ta b l e 5 6 ). 08-dec-2008 6 changed v dd minimum value from 3.0 to 2.95 v. updated number of high sink i/os in pinout. removed flash _nfpr and flash _fpr registers in table 9: general hardware register map . 30-jan-2009 7 removed preliminary status. removed vqfn32 package. added stm8s207c6, stm8s207s6. updated external interrupts in table 2 on page 11 . updated section 10: electrical characteristics . 10-jul-2009 8 document status changed from ?pre liminary data? to ?datasheet?. added lqfp64 14 x 14 mm package. added stm8s207m8, stm8s207sb , stm8s208r8, stm8s208r6, stm8s208c8, and stm8s208c6, stm8s208sb, stm8s208s8, and stm8s208s6. replaced ?can? with ?becan?. added ta b l e 3 to section 4.5: clock controller . updated section 4.8: auto wakeup counter . added becan peripheral (impacting ta bl e 1 and figure 6 ). added footnote about can_rx/tx to pinout figures 3 , 4 , and 6 . ta bl e 6 : removed ?x? from wpu column of i 2 c pins (no wpu available). added table 11: interrupt mapping .
stm8s207xx, stm8s208xx revision history doc id 14733 rev 12 101/103 10-jul-2009 8 cont?d section 10: electrical characteristics : added data for tbd values; updated table 15: voltage characteristics and table 18: general operating conditions ; updated vcap specifications in table 18 and in section 10.3.1: vcap external capacitor ; updated figure 18 ; replaced figure 19 ; updated table 35: ram and hardware registers ; updated figure 22 and figure 35 ; added figure 40: typical application with i2c bus and timing diagram . removed table 56: junction temperature range. added link between ordering information figure 49 and stm8s20xx features ta b l e 2 . 13-apr-2010 9 document status changed from ?pre liminary data? to ?datasheet?. table 2: stm8s20xxx performance line features : high sink i/o for stm8s207c8 is 16 (not 13). table 3: peripheral clock gating bit assignments in clk_pckenr1/2 registers : updated bit positions for tim2 and tim3. figure 5: lqfp 48-pin pinout : added can_tx and can_rx to pins 35 and 36; noted that these pins are available only in stm8s208xx devices. figure 7: lqfp 32-pin pinout : replaced uart2 with uart3. table 6: pin description : added footnotes concerning becan availability and uart1_rx and uart3_rx pins. table 13: option byte description : added description of stm8l bootloader option bytes to the option byte description table. added section 9: unique id (and listed this attribute in features ). section 10.3: operating conditions : added introductory text. table 18: general operating conditions : replaced ?c ext ? with ?vcap? and added data for esr and esl; removed ?low power dissipation? condition for t a . table 26: total current consumption in halt mode at vdd = 5 v : replaced max value of i dd(h) at 85 c from 30 a to 35 a for the condition ?flash in powerdown mode, hsi clock after wakeup?. table 33: hsi oscillator characteristics : updated the acc hsi factory calibrated values. functional ems (electromagnetic susceptibility) and ta b l e 4 7 : replaced ?iec 1000? with ?iec 61000?. electromagnetic interference (emi) and table 48 : replaced ?sae j1752/3? with ?iec 61967-2?. table 57: thermal characteristics : changed the thermal resistance junction-ambient value of lqfp32 (7x7 mm) from 59 c/w to 60 c/w. table 58. document revision history (continued) date revision changes
revision history stm8s207xx, stm8s208xx 102/103 doc id 14733 rev 12 14-sep-2010 10 added part number stm8s208m8 to table 1: device summary . updated "reset state" of table 5: legend/abbreviations for pinout table . added footnote 4 to table 6: pin description . table 9: general hardware register map : standardized all reset state values; updated the reset state values of rst_sr, clk_swcr, clk_hsitrimr, clk_swimc cr, iwdg_kr, and adc_drx registers; added the reset values of the can paged registers. figure 36: recommended reset pin protection : replaced 0.01 f with 0.1 f. figure 40: typical application with i2c bus and timing diagram : t w(sckh) , t w(sckl) , t r(sck) , and t f(sck) replaced by t w(sclh) , t w(scll) , t r(scl) , and t f(scl) respectively. 22-mar-2011 11 table 1: device summary : added stm8s207k8. table 2: stm8s20xxx performance line features : added stm8s207k8 device and changed the ram value of all other devices to 6 kbytes. figure 3 , figure 4 , figure 5 , and figure 7 : removed tim1_ch4 from pins 80, 64, 48, and 32 respectively. table 6: pin description : updated note 3 and added note 5 . table 9: general hardware register map : removed i2c_pecr register. section 10.3.7: reset pin characteristics : added text regarding the rest network. 10-feb-2012 12 figure 1: stm8s20xxx performance line block diagram : updated por/pdr and bor; updated linuart input; added legend. table 18: general operating conditions : updated v cap . table 26: total current consumpt ion in halt mode at vdd = 5 v : updated title, modified existing max column, and added new max column (at 125 c) with data. table 37: i/o static characteristics : added new condition and new max values for rise and fall time; added footnote 3 ; updated typ and max pull-up resistor values. section 10.3.7: reset pin characteristics : updated cross reference in text below figure 35 table 41: nrst pin characteristics : updated typ and max values of the nrst pull-up resistor. table 58. document revision history (continued) date revision changes
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